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a preliminary technical data adsp-21161n dsp microcomputer this information applies to a product under development. its characteristics and specifications are subject to change without notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. one technology way http://www.analog.com/dsp p.o. box 9106 tel: 1-800-analog-d norwood ma 02062-9106 fax: 1-781-461-3010 u.s.a . ? analog devices inc., 2000 rev. pra summary ? high performance 32-bit dsp?applications in audio, medical, military, wireless communica- tions, graphics, imaging, motor-control, and te- lephony super harvard architecture?four independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-overhead i/o code-compatible to all other sharc family dsps single-instruction-multiple-data (simd) com- putational architecture?two 32-bit ieee float- ing-point computation units, each with a multiplier, alu, shifter, and register file serial ports offer i 2 s support via 8 programma- ble and simultaneous receive and transmit pins, which supports up to 16 transmit or 16 receive channels of audio integrated peripherals?integrated i/o proces- sor, 1 mbit on-chip dual-ported sram, sdram controller, glueless multiprocessing features, and i/o ports (serial, link, external bus, spi, & jtag) adsp-21161n supports 32-bit fixed, 32-bit float, and 40-bit floating point formats. key features 100 mhz (10 ns) core instruction rate single-cycle instruction execution, including simd operations in both computational units 600 mflops peak and 400 mflops sustained performance 225-ball 17x17mm pbga package 1 mbit on-chip dual-ported sram (0.5 mbit block 0, 0.5 mbit block 1) for independent ac- cess by core processor and dma figure 1 adsp-21161n functional block diagram spi ports (1) serial ports (4) link ports (2) dma controller mult alu barrel shifter data register file (pey) 16 x 40-bit mult alu barrel shifter data register file (pex) 16 x 40-bit 5 16 20 4 iop registers ( memory mapped) control, status, & data buffers i/o processor timer instruction cache 32 x 48-bit addr data data data addr addr data addr two independent dual-ported blocks processor port i/o port b l o c k 0 b l o c k 1 dual-ported sram host port addr bus mux ioa 18 iod 64 multiprocessor interface external port data bus mux 32 24 32 pm address bus dm address bus pm data bus dm data bus bus connect (px) dag1 8x4x32 32 64 64 core processor program sequencer dag2 8x4x32 jtag test & emulation 6 gpio flags sdram controller 12 8
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 2 rev. pra key features (continued) 400 million fixed-point macs sustained performance dual data address generators (dags) with modulo and bit-reverse addressing zero-overhead looping with single-cycle loop setup, providing efficient program sequencing ieee 1149.1 jtag standard test access port and on-chip emulation single instruction multiple data (simd) architecture provides: two computational processing elements concurrent execution--each processing element executes the same instruction, but oper- ates on different data code compatibility--at assembly level, uses the same instruction set as other sharc dsps parallelism in busses and computational units allows: single-cycle execution (with or without simd) of: a multiply operation, an alu opera- tion, a dual memory read or write, and an instruction fetch transfers between memory and core at up to four 32-bit floating- or fixed-point words per cycle, sustained 1.6 gigabytes/second bandwidth accelerated fft butterfly computation through a multiply with add and subtract dma controller supports: 14 zero-overhead dma channels for transfers between adsp-21161n internal memory and external memory, external peripherals, host processor, serial ports, link ports or serial peripheral interface (spi) interface 64-bit background dma transfers at core clock speed, in parallel with full-speed proces- sor execution 800 mbytes/s transfer rate over iop bus host processor interface to 8-, 16- and 32-bit microprocessors, the host can directly read/write adsp-21161n iop registers. 32-bit (or up to 48-bit) wide synchronous external port provides: glueless connection to asynchronous, sbsram and sdram external memories memory interface supports programmable wait state generation and wait mode for off-chip memory up to 50 mhz operation for non-sdram accesses 1:2, 1:3, 1:4, 1:6, 1:8 clock in to core clock frequency multiply ratios 24-bit address, 32-bit data bus. 16 additional data lines via multiplexed link port data pins allow complete 48-bit wide data bus for single-cycle external instruction execution direct reads and writes of iop registers from host or other 21161n dsps 64 mega-word address range for off-chip sram and sbsram memories 32-48, 16-48, 8-48 execution packing for executing instruction directly from 32-bit, 16-bit, or 8-bit wide external memories 32-48, 16-48, 8-48, 32-32/64, 16-32/64, 8-32/64, data packing for dma transfers di- rectly from 32-bit, 16-bit, or 8-bit wide external memories to and from internal 32-, 48-, or 64-bit internal memory can be configured to have 48-bit wide external data bus possible, if link ports are not
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 3 rev. pra used. the link port data lines are multiplexed with the data lines d0 to d15 and is en- abled through control bits in syscon sdram controller for glueless interface to low cost external memory zero wait state, 100 mhz operation for most accesses extended external memory banks (64 m-words) for sdram accesses page sizes up to 2048 words an sdram controller supports sdram in any and all memory banks support for interface to run at core clock & half the core clock frequency support for 16 mbits, 64 mbits, 128 mbits, and 256 mbits with sdram data bus con- figurations of x4, x8 and x16 254 mega-word address range for off-chip sdram memory multiprocessing support provides: glueless connection for scalable dsp multiprocessing architecture distributed on-chip bus arbitration for parallel bus connect of up to six adsp-21161ns, global memory and a host two 8-bit wide link ports for point-to-point connectivity and array multiprocessing be- tween adsp-21161ns 400 mbytes/s transfer rate over parallel bus 200 mbytes/s transfer rate over link ports serial ports provide: four 50 mbit/s synchronous serial ports with companding hardware 8 bi-directional serial data pins, configurable as either a transmitter or receiver i 2 s support, programmable direction for 8 simultaneous receive and transmit channels, or up to either 16 transmit channels or 16 receive channels. tdm support for t1 and e1 interfaces, and 128 tdm channel support for newer tele- phony interfaces such as h.100/h.110 companding selection on a per channel basis in tdm mode serial peripheral interface (spi) slave serial boot through spi from a master spi device full-duplex operation master-slave mode multi-master support open drain outputs programmable baud rates, clock polarities and phases 12 programmable i/o pins
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 4 rev. pra general description the adsp-21161n sharc dsp is the first low-cost derivative of the adsp-21160 featuring analog devices ? super harvard architecture. easing portability, the adsp-21161n is source code compatible with the adsp-21160 and with first generation adsp-2106x sharcs in sisd (single instruction, single data) mode. like other sharcs, the adsp-21161n is a 32-bit processor that is optimized for high performance dsp applications. the adsp-21161n includes a 100 mhz core, a dual-ported on-chip sram, an integrated i/o processor with multiprocessing support, and multiple internal busses to eliminate i/o bottlenecks. the adsp-21161n offers a single-instruction-multiple-data (simd) architecture, which was first offered in the adsp-21160. using two computational units (adsp-2106x sharcs have one), the adsp-21161n can double cycle performance versus the adsp-2106x on a range of dsp algorithms. fabricated in a state of the art, high speed, low power cmos process, the adsp-21161n has a 10 ns instruction cycle time. with its simd computational hardware running at 100 mhz, the adsp-21161n can perform 600 million math operations per second. table 1 shows performance benchmarks for the adsp-21161n. the adsp-21161n continues sharc ? s industry leading standards of integration for dsps, combining a high performance 32-bit dsp core with integrated, on-chip system features. these features include a 1 mbit dual ported sram memory, host processor interface, i/o processor that supports 14 dma channels, four serial ports, two link ports, sdram controller, spi interface, external parallel bus, and glueless multiprocessing. figure 1 on page 1 shows a block diagram of the adsp-21161n, illustrating the following architectural features: two processing elements, each made up of an alu, multiplier, shifter and data register file data address generators (dag1, dag2) program sequencer with instruction cache pm and dm buses capable of supporting four 32-bit data transfers between memory and the core every core processor cycle interval timer table 1 adsp-21161n benchmarks (at 100 mhz) benchmark algorithm speed (at 100 mhz) 1024 point complex fft (radix 4, with reversal) 92 s fir filter (per tap) 5 ns iir filter (per biquad) 20 ns matrix multiply (pipelined) [3x3] * [3x1] [4x4] * [4x1] 45 ns 80 ns divide (y/x) 30 ns inverse square root 45 ns
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 5 rev. pra on-chip sram (1 mbit) sdram controller for glueless interface to sdrams external port that supports: interfacing to off-chip memory peripherals glueless multiprocessing support for six adsp-21161n sharcs host port read/write of iop registers dma controller four serial ports two link ports spi-compatible interface jtag test access port 12 general purpose i/o pins figure 2 shows a typical single-processor system. a multi-processing system appears in figure 5 on page 11 . figure 2 adsp-21161n system dma device (optional) data clkout dmar 1-2 dmag 1-2 redy addr data host processor in ter fa ce (optional) 3 12 clock clkin xtal irq 2-0 2 clk_cfg1-0 eboot lboot fla g 11-0 tim ex p clkdbl reset jta g 7 sbts adsp-21161n bms lin k devices (2 m a x) (optional) lxc lk lxa c k lxdat 7-0 sc lk0 d0b d0a fs0 serial device (optional) cs boot eprom (optional) addr memory and peripherals (optional) oe data cs rd ras ack br 1-6 rpba id 2-0 pa hbg hbr sdwe ms 3-0 wr data 47-16 data addr cs ack we addr 23-0 data c ontrol a ddress brst sdram (optional) sc lk1 d1b d1a fs1 serial device (optional) sc lk2 d2b d2a fs2 serial device (optional) sc lk3 d3b d3a fs3 serial device (optional) spiclk miso mosi spds spi- compatible device (host or slave) (optional) data cas ras dqm we addr cs a10 cke clk dqm cas
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 6 rev. pra adsp-21161n family core architecture the adsp-21161n includes the following architectural features of the adsp-21100 family core. the adsp-21161n is code compatible at the assembly level with the adsp-21160, adsp-21060, adsp-21061, and adsp-21062 and adsp-21065l. simd computational engine the adsp-21161n contains two computational processing elements that operate as a single instruction multiple data (simd) engine. the processing elements are referred to as pex and pey and each contains an alu, multiplier, shifter and register file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. when this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. this architecture is efficient at executing math intensive dsp algorithms. entering simd mode also has an effect on the way data is transferred between memory and the processing elements. when in simd mode, twice the data bandwidth is required to sustain computational operation in the processing elements. because of this requirement, entering simd mode also doubles the bandwidth between memory and the processing elements. when using the dags to transfer data in simd mode, two data values are transferred with each access of memory or the register file. independent, parallel computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier and shifter. these units perform single-cycle instructions. the three units within in each processing element are arranged in parallel, maximizing computational throughput. single multi-function instructions execute parallel alu and multiplier operations. in simd mode, the parallel alu and multiplier operations occur in both processing elements. these computation units support ieee 32-bit single-precision floating-point, 40-bit extended precision floating-point, and 32-bit fixed-point data formats. data register file a general purpose data register file is contained in each processing element. the register files transfer data between the computation units and the data buses, and store intermediate results. these 10-port, 32-register (16 primary, 16 secondary) register files, combined with the adsp-21100 enhanced harvard architecture, allow unconstrained data flow between computation units and internal memory. the registers in pex are referred to as r0-r15 and in pey as s0-s15. single-cycle fetch of instruction and four operands the adsp-21161n features an enhanced harvard architecture in which the data memory (dm) bus transfers data and the program memory (pm) bus transfers both instructions and data (see figure 1 on page 1 ). with the adsp-21161n ? s separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and an instruction (from the cache), all in a single cycle. instruction cache the adsp-21161n includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. the cache is selective ? only the instructions whose fetches conflict with pm bus data accesses are cached. this cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates and fft butterfly processing.
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 7 rev. pra data address generators with hardware circular buffers the adsp-21161n ? s two data address generators (dags) are used for indirect addressing and let you implement circular data buffers in hardware. circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and fourier transforms. the two dags of the adsp-21161n contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). the dags automatically handle address pointer wrap-around, reducing overhead, increasing performance, and simplifying implementation. circular buffers can start and end at any memory location. flexible instruction set the 48-bit instruction word accommodates a variety of parallel operations, for concise programming. for example, the adsp-21161n can conditionally execute a multiply, an add, and a subtract in both processing elements, while branching, all in a single instruction. adsp-21161n memory and i/o interface features augmenting the adsp-21100 family core, the adsp-21161n adds the following architectural features: dual-ported on-chip memory the adsp-21161n contains one megabit of on-chip sram, organized as two blocks of 0.5 mbits each, which can be configured for different combinations of code and data storage. each memory block is dual-ported for single-cycle, independent accesses by the core processor and i/o processor. the dual-ported memory in combination with three separate on-chip buses allow two data transfers from the core and one from the i/o processor, in a single cycle. on the adsp-21161n, the memory can be configured as a maximum of 32k words of 32-bit data, 64k words of 16-bit data, 21.25k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to one megabit. all of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. a 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. conversion between the 32-bit floating-point and 16-bit floating-point formats is done in a single instruction. while each memory block can store combinations of code and data, accesses are most efficient when one block stores data, using the dm bus for transfers, and the other block stores instructions and data, using the pm bus for transfers. using the dm bus and pm bus in this way, with one dedicated to each memory block, assures single-cycle execution with two data transfers. in this case, the instruction must be available in the cache.
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 8 rev. pra figure 3 adsp-21161n memory map off-chip memory and peripherals interface the adsp-21161n ? s external port provides the processor ? s interface to off-chip memory and peripherals. the 64-megaword off-chip address space (254-megaword if all sdram) is included in the adsp-21161n ? s unified address space. the separate on-chip buses ? for pm addresses, pm data, dm addresses, dm data, i/o addresses, and i/o data ? are multiplexed at the external port to create an external system bus with a single 24-bit address bus and a single 32-bit data bus. every access to external memory is based on an address that fetches a 32-bit word. when fetching an instruction from external memory, two 32-bit data locations are being accessed for packed instructions. unused link port lines can also be used as additional data lines data[0]-data[15], allowing single cycle execution of instructions from external memory at up to 100 mhz. figure 4 on page 10 shows the alignment of various accesses to external memory. the external port supports asynchronous, synchronous, and synchronous burst accesses. synchronous burst sram can be interfaced gluelessly. the adsp-21161n also can interface gluelessly to sdram. addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. separate control lines are also generated for simplified addressing of page-mode dram. the adsp-21161n provides programmable memory wait states and external memory acknowledge controls to allow interfacing to memory and peripherals with variable access, hold, and disable time requirements. 0x000a 0000 - 0x000a 7fff (blk 1) 0x0002 8000 - 0x0002 9fff (blk 1) 0x0005 0000 - 0x0005 3fff (blk 1) 0x0010 0000 - 0x0011 ffff 0x0004 0000 - 0x0004 3fff (blk 0) 0x0008 0000 - 0x0008 7fff (blk 0) 0x0012 0000 - 0x0013 ffff 0x0014 0000 - 0x0015 ffff 0x0016 0000 - 0x0017 ffff 0x001a 0000 - 0x001b ffff 0x001f ffff 0x001c ffff 0x0000 0000 - 0x0001 ffff 0x0002 0000 - 0x0002 1fff (blk 0) 0x0020 0000 bank 1 ! ! ! ! ms 0 * bank 2 ! ! ! ! ms 1 * bank 3 ! ! ! ! ms 2 * ! ! ! ! ms 3 * memory internal memory space iop registers iop registers of adsp-21161n with id=001 long word addressing short word addressing iop registers of adsp-21161n with id=010 iop registers of adsp-21161n with id=100 iop registers of adsp-21161n with id=011 iop registers of adsp-21161n with id=101 iop registers of adsp-21161n with id=110 normal word addressing address reserved multi- processor space bank 0 0x03ff ffff (sdram) 0x00ff ffff (non-s dram) 0x0400 0000 0x07ff ffff (sdram) 0x04ff ffff (non-s dram) 0x0800 0000 0x0bff ffff (s dram) 0x08ff ffff (non-s dram) 0x0c00 0000 0x0fff ffff (s dram) 0x0cff ffff (non-s dram) external memory space *bank sizes are fixed
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 9 rev. pra sdram interface the sdram interface enables the adsp-21161n to transfer data to and from synchronous dram (sdram) at the core clock frequency or one-half the core clock frequency. the synchronous approach, coupled with the core clock frequency, supports data transfer at a high throughput ? up to 400 mbytes/sec. for x32 transfers and 600 mbytes/sec. for x48 transfers. the sdram interface provides a glueless interface with standard sdrams ? 16 mb, 64 mb, 128 mb, and 256 mb ? and includes options to support additional buffers between the adsp-21161n and sdram. the sdram interface is extremely flexible and provides capability for connecting sdrams to any one of the adsp-21161n ? s four external memory banks, with up to all four banks mapped to sdram. systems with several sdram devices connected in parallel may require buffering to meet overall system timing requirements. the adsp-21161n supports pipelining of the address and control signals to enable such buffering between itself and multiple sdram devices. dma controller the adsp-21161n ? s on-chip dma controller allows zero-overhead data transfers without processor intervention. the dma controller operates independently and invisibly to the processor core, allowing dma operations to occur while the core is simultaneously executing its program instructions. dma transfers can occur between the adsp-21161n ? s internal memory and external memory, external peripherals, or a host processor. dma transfers can also occur between the adsp-21161n ? s internal memory and its serial ports, link ports, or the serial peripheral interface (spi)-compatible port. external bus packing and unpacking of 16-, 32-, 48-, or 64-bit words in internal memory is performed during dma transfers from either 8-, 16-, or 32-bit wide external memory. fourteen channels of dma are available on the adsp-21161n ? two are shared between the spi interface and the link ports, eight via the serial ports, and four via the processor ? s external port (for either host processor, other adsp-21161ns, memory or i/o transfers). programs can be downloaded to the adsp-21161n using dma transfers. asynchronous off-chip peripherals can control two dma channels using dma request/grant lines (dmar 1-2 , dmag 1-2 ). other dma features include interrupt generation upon completion of dma transfers, two-dimensional dma, and dma chaining for automatic linked dma transfers.
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 10 rev. pra figure 4 adsp-21161n external data alignment options multiprocessing the adsp-21161n offers powerful features tailored to multi-processing dsp systems. the external port and link ports provide integrated glueless multiprocessing support. the external port supports a unified address space (see figure 3 on page 8 ) that allows direct interprocessor accesses of each adsp-21161n ? s internal memory-mapped (i/o processor) registers. all other internal memory can be indirectly accessed via dma transfers initiated via the programming of the iop dma parameter and control registers. distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing up to six adsp-21161ns and a host processor. master processor change over incurs only one cycle of overhead. bus arbitration is selectable as either fixed or rotating priority. bus lock allows indivisible read-modify-write sequences for semaphores. a vector interrupt is provided for interprocessor commands. maximum throughput for interprocessor data transfer is 400 mbytes/s over the external port. two link ports provide for a second method of multiprocessing communications. each link port can support communications to another adsp-21161n. a large multiprocessor system can be constructed in a 2d fashion, using the link ports. the adsp-21161n running at 100 mhz has a maximum throughput for interprocessor communications over the links of 200 mbytes per second. you can use the link ports and cluster multiprocessing concurrently or independently. 47 48-bit instruction fetch (no packing) extra data lines data[15-0] are only accessible if link ports are disabled. enable these additional data lines by setting ipack[1:0] = 01 in syscon. 0 7 8 15 16 23 24 31 32 39 40 float or fixed , d31-d0 , 32-bit packed 16-bit packed dma data 16-bit packed instruction execution prom boot data 47-16 l1data[7:0] l0data[7:0] data 15-8 data 7-0 8-bit packed dma data 8-bit packed instruction execution 32-bit packed instruction data 15-0
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 11 rev. pra figure 5 adsp-21161n shared memory multiprocessing system ack oe addr data cs we global memory and peripherals (optional) control adsp-2116x #1 addr 23-0 data 47-16 control adsp-21161 #3 id 2-0 reset clkin 3 adsp-21161 #4 clock addr data sdram (optional) cs addr data boot eprom (optional) id 2-0 reset clkin control addres s data control addres s data addr 23-0 data 47-16 control adsp-21161 #2 id 2-0 reset clkin 2 1 addr data host processor interface (optional) we ras cas dqm clk a10 cke cs data 47-16 sdwe ras cas dqm sdclk[1-0] sda10 sdcke br 6-2 rd ms 3-0 sbts clkout cs ack br1 redy hbg hbr wr bms addr 23-0 reset
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 12 rev. pra link ports the adsp-21161n features two 8-bit link ports that provide additional i/o capabilities. with the capability of running at 100 mhz rates, each link port can support 100 mbytes/s. link port i/o is especially useful for point-to-point interprocessor communication in multiprocessing systems. the link ports can operate independently and simultaneously, with a maximum data throughput of 200 mbytes/s. link port data is packed into 48- or 32-bit words and can be directly read by the core processor or dma-transferred to on-chip memory. each link port has its own double-buffered input and output registers. clock/acknowledge handshaking controls link port transfers. transfers are programmable as either transmit or receive. serial ports the adsp-21161n features four synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. each serial port is made up of two data lines, a clock and frame sync. the data lines can be programmed to be either transmit or receive. the serial ports can operate up to half the clock rate of the core, providing each with a maximum data rate of 50 mbit/s. the serial data pins can be programmable as either a transmitter or receiver, providing greater flexibility for serial communications. serial port data can be automatically transferred to and from on-chip memory via a dedicated dma. each of the serial ports offers a time division multiplex (tdm) multichannel mode, where two serial ports are tdm transmitters and two serial ports are tdm receivers (sport0 rx paired with sport2 tx, sport1 rx paired with sport3 tx). each of the serial ports also support the i 2 s protocol (an industry standard interface commonly used by audio codecs, adcs and dacs), with two data pins, allowing four i 2 s channels (using 2 i 2 s stereo devices) per serial port, with a maximum of up to 16 i 2 s channels. the serial ports can operate with little-endian or big-endian transmission formats, with word lengths selectable from 3 bits to 32 bits. for i 2 s mode, data-word lengths are selectable between 8 bits and 32 bits. they offer selectable synchronization and transmit modes as well as optional -law or a-law companding. serial port clocks and frame syncs can be internally or externally generated. serial peripheral (compatible) interface serial peripheral interface (spi) is an industry standard synchronous serial link, enabling the adsp-21161n spi-compatible port to communicate with other spi-compatible devices. spi is a 4-wire interface consisting of two data pins, one device select pin, and one clock pin. it is a full-duplex synchronous serial interface, supporting both master and slave modes. it can operate in a multi-master environment by interfacing with up to 4 other spi-compatible devices, either acting as a master or slave device. the adsp-21161n spi-compatible peripheral implementation also supports programmable baud rate and clock phase/polarities. the adsp-21161n spi-compatible port supports the use of open drain drivers to support the multi-master scenario and to avoid data contention. host processor interface the adsp-21161n host interface allows easy connection to standard microprocessor buses, either 8-bit, 16-bit, or 32-bit, with little additional hardware required. the host interface is accessed through the adsp-21161n ? s external port and is memory-mapped into the unified address space. four channels of dma are available for the host interface; code and data transfers are accomplished with low software overhead. the host processor requests the adsp-21161n ? s external bus with the host bus request (hbr ), host bus grant (hbg ), and ready (redy) signals. the host can directly read and write the internal iop registers of the adsp-21161n, and can access the dma channel setup and mailbox registers. dma setup via a host would allow it to access any internal memory address via dma transfers. vector interrupt support provides efficient execution of host commands.
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 13 rev. pra general purpose i/o ports the adsp-21161n also contains twelve programmable, general purpose i/o pins that can function as either input or output. as output, these pins can signal peripheral devices; as input, these pins can provide the test for conditional branching. program booting the internal memory of the adsp-21161n can be booted at system power-up from either an 8-bit eprom, a host processor, the spi interface, or through one of the link ports. selection of the boot source is controlled by the boot memory select (bms ), eboot (eprom boot), and link/host boot (lboot) pins. 8-, 16-, or 32-bit host processors can also be used for booting. phased locked loop and clkin double enable the adsp-21161n uses an on-chip phase locked loop (pll) to generate the internal clock for the core. the clk_cfg[1:0] pins are used to select ratios of 2:1, 3:1, and 4:1. in addition to the pll ratios, an additional clkdbl pin can be used for additional clock ratio options. the (1x/2x clkin) rate set by the clkdbl pin determines the rate of the pll input clock and the rate at which the synchronous external port operates. with the combination of clk_cfg[1:0] and clkdbl , ratios of 2:1, 3:1, 4:1, 6:1, and 8:1 between the core and clkin are supported. see also figure 8 on page 28 . power supplies the adsp-21161n has separate power supply connections for the internal (vddint), external (vddext), and analog (avdd/agnd) power supplies. the internal and analog supplies must meet the 1.8v requirement. the external supply must meet the 3.3v requirement. all external supply pins must be connected to the same supply note that the analog supply (av dd ) powers the adsp-21161n ? s clock generator pll. to produce a stable clock, you must provide an external circuit to filter the power input to the av dd pin. place the filter as close as possible to the pin. for an example circuit, see figure 6. to prevent noise coupling, use a wide trace for the analog ground (agnd) signal and install a decoupling capacitor as close as possible to the pin. figure 6 analog power (av dd ) filter circuit development tools the adsp-21161n is supported by a complete set of visualdsp ? software and hardware development tools, including the analog devices white mountain line of jtag emulator and development software. the same analog devices white mountain line of jtag emulator hardware that you use for the adsp-21060/62/61/65l and adsp-21160, also fully emulates the adsp-21161n. v ddint av dd agnd 0.01 f 0.1 f 10 ?
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 14 rev. pra both the sharc development tools family and the visualdsp integrated project management and debugging environment support the adsp-21161n. the visualdsp project management environment enables you to develop and debug an application from within a single, integrated program. the sharc development tools include an easy to use assembler that is based on an algebraic syntax; an assembly library/librarian; a linker; a loader; a cycle-accurate, instruction-level simulator; a c compiler; and a c run-time library that includes dsp and mathematical functions. debugging both c and assembly programs with the visual dsp debugger, enables you to: view mixed c and assembly code insert break points set conditional breakpoints on registers, memory, and stacks trace instruction execution profile program execution fill and dump memory perform source-level debugging create custom debugger windows the visualdsp ide lets you define and manage dsp software development. its dialog boxes and property pages enable you to configure and manage all of the sharc development tools, including the syntax highlighting in the visualdsp editor. this capability lets you: control how the development tools process inputs and generate outputs. maintain a one-to-one correspondence with the tool ? s command line switches. analog devices white mountain line of jtag emulators use the ieee 1149.1 jtag test access port of the adsp-21161n processor to monitor and control the target board processor during emulation. jtag emulators provide emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. the processor's jtag interface ensures the emulator will not affect target system loading or timing. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the sharc processor family. hardware tools include sharc pc plug-in cards, multiprocessor sharc vme boards, a daughter board, and modules with multiple sharcs and additional memory. third party software tools include dsp libraries, real-time operating systems, and block diagram design tools. additional information this data sheet provides a general overview of the adsp-21161n architecture and functionality. for detailed information on the adsp-21100 family core architecture and instruction set, refer to the adsp-21161n technical specification . pin function descriptions adsp-21161n pin definitions are listed below. inputs identified as synchronous (s) must meet timing requirements with respect to clkin (or with respect to tck for tms, tdi). inputs identified as asynchronous (a) can be asserted asynchronously to clkin (or to tck for trst ). unused inputs should be tied or pulled to vddint or gnd, except for addr 23-0 , data 47-16 , flag 11-0 , and inputs that have internal pull-up or pull-down resistors (pa , ack, brst, clkout,
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 15 rev. pra ms 3-0 , rd , wr , dmar x , dmag x , dxa, dxb, sclkx, lxdat 7-0 , lxclk, lxack, tms, trst and tdi)--these pins can be left floating. these pins have a logic-level hold circuit (only enabled on the adsp-21161n with id2-0=00x) that prevents input from floating internally. the following symbols appear in the type column of table 2 : a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open drain, and t = three-state (when sbts is asserted or when the adsp-21161n is a bus slave). table 2 pin descriptions pin type function addr 23-0 i/o/t external bus address . the adsp-21161n outputs addresses for external memory and peripherals on these pins. in a multiprocessor system the bus master outputs addresses for read/writes of the iop registers of other adsp-21161ns while all other internal memory resources can be accessed indirectly via dma control (that is, accessing iop dma param- eter registers). the adsp-21161n inputs addresses when a host proces- sor or multiprocessing bus master is reading or writing its iop registers. a keeper latch on the dsp ? s addr 23-0 pins maintains the input at the level it was last driven (only enabled on the adsp-21161n with id2-0=00x). data 47-16 i/o/t external bus data . the adsp-21161n inputs and outputs data and instructions on these pins. pull-up resistors on unused data pins are not necessary. a keeper latch on the dsp ? s data 47-16 pins maintains the input at the level it was last driven (only enabled on the adsp-21161n with id2-0=00x). note: data[15:8] pins (multiplexed with l1data[7:0]) can also be used to extend the data bus if the link ports are disabled and will not be used. in addition, data[7:0] pins (multiplexed with l0data[7:0]) can also be used to extend the data bus if the link ports are not used. this allows execution of 48-bit instructions from external sbsram (system clock speed-external port), sram (system clock speed-external port) and sdram (core clock or one-half the core clock speed). the ipackx instruction packing mode bits in syscon should be set correctly (ipack 1-0 = 0x1) to enable this full instruction width/no-packing mode of operation. ms 3-0 i/o/t memory select lines . these outputs are asserted (low) as chip selects for the corresponding banks of external memory. memory bank sizes are fixed to 16 mwords for non-sdram and 64 mwords for sdram. the ms 3-0 outputs are decoded memory address lines. in asynchronous access mode, the ms 3-0 outputs transition with the other address outputs. in synchronous access modes, the ms 3-0 outputs assert with the other address lines; however, they de-assert after the first clkin cycle in which ack is sampled asserted. in a multiprocessor systems, the ms x signals are tracked by slave sharcs.
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 16 rev. pra rd i/o/t memory read strobe. rd is asserted whenever adsp-21161n reads a word from external memory or from the iop registers of other adsp-21161ns. external devices, including other adsp-21161ns, must assert rd for reading from a word of the adsp-21161n iop regis- ter memory. in a multiprocessing system, rd is driven by the bus master. wr i/o/t memory write low strobe. wr is asserted when adsp-21161n writes a word to external memory or iop registers of other adsp-21161ns. external devices must assert wr for writing to adsp-21161n's iop registers. in a multiprocessing system, wr is driven by the bus master. brst i/o/t sequential burst access. brst is asserted by adsp-21161n to indicate that data associated with consecutive addresses is being read or written. a slave device samples the initial address and increments an internal address counter after each transfer. the incremented address is not pipelined on the bus. a master adsp-21161n in a multiprocessor environment can read slave external port buffers (epbx) using the burst protocol. brst is asserted after the initial access of a burst transfer. it is asserted for every cycle after that, except for the last data request cycle (denoted by rd or wr asserted and brst negated). a keeper latch on the dsp ? s brst pin maintains the input at the level it was last driven (only enabled on the adsp-21161n with i d2-0=00x). ack i/o/s memory acknowledge . external devices can de-assert ack (low) to add wait states to an external memory access. ack is used by i/o devices, memory controllers, or other peripherals to hold off completion of an external memory access. the adsp-21161n deasserts ack as an output to add wait states to a synchronous access of its iop registers. sbts i/s suspend bus & three-state . external devices can assert sbts (low) to place the external bus address, data, selects, and strobes in a high imped- ance state for the following cycle. if the adsp-21161n attempts to access external memory while sbts is asserted, the processor will halt and the memory access will not be completed until sbts is de-asserted. sbts should only be used to recover from host processor/adsp-21161n dead- lock. cas i/o/t sdram column access strobe. in conjunction with ras , ms x, sdwe , sdclkx, and sometimes sda10, defines the operation for the sdram to perform. ras i/o/t sdram row access strobe. in conjunction with cas , ms x, sdwe , sdclkx, and sometimes sda10, defines the operation for the sdram to perform. sdwe i/o/t sdram write enable. in conjunction with cas , ras , msx , sdclkx, and sometimes sda10, defines the operation for the sdram to perform. table 2 pin descriptions (continued) pin type function
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 17 rev. pra dqm o/t sdram data mask. in write mode, dqm has a latency of zero and is used during a precharge command and during sdram power-up initial- ization. sdclk0 i/o/s/t sdram clock output 0. clock for sdram devices. sdclk1 o/s/t sdram clock output 1. additional clock for sdram devices. for systems with multiple sdram devices, handles the increased clock load requirements, eliminating need of off-chip clock buffers. either sdclk1 or both sdclkx pins can be three-stated. sdcke i/o/t sdram clock enable. enables and disables the clk signal. for details, see the data sheet supplied with your sdram device. sda10 o/t sdram a10 pin. enables applications to refresh an sdram in paral- lel with a non-sdram accesses or host accesses. irq2-0 i/a interrupt request lines. these are sampled on the rising edge of clkin and may be either edge-triggered or level-sensitive. flag11-0 i/o/a flag pins . each is configured via control bits as either an input or output. as an input, it can be tested as a condition. as an output, it can be used to signal external peripherals. timexp o timer expired . asserted for four clkin cycles when the timer is enabled and tcount decrements to zero. hbr i/a host bus request . must be asserted by a host processor to request con- trol of the adsp-21161n's external bus. when hbr is asserted in a multiprocessing system, the adsp-21161n that is bus master will relin- quish the bus and assert hb g . to relinquish the bus, the adsp-21161n places the address, data, select, and strobe lines in a high impedance state. hbr has priority over all adsp-21161n bus requests (br6-1 ) in a mul- tiprocessing system. hbg i/o host bus grant . acknowledges an hbr bus request, indicating that the host processor may take control of the external bus. hbg is asserted (held low) by the adsp-21161n until hbr is released. in a multipro- cessing system, hbg is output by the adsp-21161n bus master and is monitored by all others. cs i/a chip select . asserted by host processor to select the adsp-21161n. redy o (o/d) host bus acknowledge . the adsp-21161n de-asserts redy (low) to add waitstates to a host access of its iop registers when cs and hbr inputs are asserted. dmar1 i/a dma request 1 (dma channel 11). asserted by external port devices to request dma services. table 2 pin descriptions (continued) pin type function
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 18 rev. pra dmar2 i/a dma request 2 (dma channel 12). asserted by external port devices to request dma services. dmag1 o/t dma grant 1 (dma channel 11). asserted by adsp-21161n to indi- cate that the requested dma starts on the next cycle. driven by bus mas- ter only. dmag2 o/t dma grant 2 (dma channel 12). asserted by adsp-21161n to indi- cate that the requested dma starts on the next cycle. driven by bus mas- ter only. br 6-1 i/o/s multiprocessing bus requests . used by multiprocessing adsp-21161ns to arbitrate for bus mastership. an adsp-21161n only drives its own br x line (corresponding to the value of its id2-0 inputs) and monitors all others. in a multiprocessor system with less than six adsp-21161ns, the unused br x pins should be pulled high; the proces- sor's own br x line must not be pulled high or low because it is an output. bmstr o bus master output. in a multiprocessor system, indicates whether the adsp-21161n is current bus master of the shared external bus. the adsp-21161n drives bmstr high only while it is the bus master. in a single-processor system (id = 000), the processor drives this pin high. id2-0 i multiprocessing id . determines which multiprocessing bus request (br1 - br6) is used by adsp-21161n. id = 001 corresponds to br1, id = 010 corresponds to br2, and so on. use id = 000 or id = 001 in single-processor systems. these lines are a system configuration selection that should be hardwired or only changed at reset. rpba i/s rotating priority bus arbitration select . when rpba is high, rotating priority for multiprocessor bus arbitration is selected. when rpba is low, fixed priority is selected. this signal is a system configuration selection that must be set to the same value on every adsp-21161n. if the value of rpba is changed during system operation, it must be changed in the same clkin cycle on every adsp-21161n. pa i/o/t priority access . asserting its pa pin allows an adsp-21161n bus slave to interrupt background dma transfers and gain access to the external bus. pa is connected to all adsp-21161ns in the system. if access prior- ity is not required in a system, the pa pin should be left unconnected. dxa i/o data transmit or receive channel a (serial ports 0, 1, 2, 3). each dxa pin has a 50 k ? internal pull-up resistor. bidirectional data pin. this signal can be configured as an output to transmit serial data, or as an input to receive serial data. dxb i/o data transmit or receive channel b (serial ports 0, 1, 2, 3). each dxb pin has a 50 k ? internal pull-up resistor. bidirectional data pin. this signal can be configured as an output to transmit serial data, or as an input to receive serial data. table 2 pin descriptions (continued) pin type function
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 19 rev. pra sclkx i/o transmit/receive serial clock (serial ports 0, 1, 2, 3). each sclk pin has a 50 k ? internal pull-up resistor. this signal can be either internally or externally generated. fsx i/o transmit or receive frame sync (serial ports 0, 1, 2, 3). the frame sync pulse initiates shifting of serial data. this signal is either generated internally or externally. it can be active high or low or an early or a late frame sync, in reference to the shifting of serial data. spiclk i/o serial peripheral interface clock signal . driven by the master, this sig- nal controls the rate at which data is transferred. the master may trans- mit data at a variety of baud rates. spiclk cycles once for each bit transmitted. spiclk is a gated clock that is active during data transfers, only for the length of the transferred word. slave devices ignore the serial clock if the slave select input is driven inactive (high). spiclk is used to shift out and shift in the data driven on the miso and mosi lines. the data is always shifted out on one clock edge of the clock and sampled on the opposite edge of the clock. clock polarity and clock phase relative to data are programmable into the spictl control register and define the transfer format. spids i serial peripheral interface slave device select. an active low signal used to enable slave devices. this input signal behaves like a chip select, and is provided by the master device for the slave devices. in multi-master mode spids signal can be asserted to a master device to signal that an error has occurred, as some other device is also trying to be the master device. if asserted low when the device is in master mode, it is considered a multi-master error. for a single-master, multiple-slave configuration where flag 3-0 are used, this pin must be tied high to vddint. for adsp-21161n to adsp-21161n spi interaction, any of the master adsp-21161n's flag 3-0 pins can be used to drive the spids signal on the adsp-21161n spi slave device. mosi i/o spi master out slave. if the adsp-21161n is configured as a master, the mosi pin becomes a data transmit (output) pin, transmitting output data. if the adsp-21161n is configured as a slave, the mosi pin becomes a data receive (input) pin, receiving input data. in an adsp-21161n spi interconnection, the data is shifted out from the mosi output pin of the master and shifted into the mosi input(s) of the slave(s). miso i/o spi master in slave out. if the adsp-21161n is configured as a mas- ter, the miso pin becomes a data receive (input) pin, receiving input data. if the adsp-21161n is configured as a slave, the miso pin becomes a data transmit (output) pin, transmitting output data. in an adsp-21161n spi interconnection, the data is shifted out from the miso output pin of the slave and shifted into the miso input pin of the master. note: only one slave is allowed to transmit data at any given time. table 2 pin descriptions (continued) pin type function
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 20 rev. pra lxdat7-0 [data15-0] i/o [i/o/t] link port data (link ports 0-1). each lxdat pin has a 50 k ? internal pull-down resistor that is enabled or disabled by the lpdrd bit of the lctl0-1 register. note: l1data[7:0] are multiplexed with the data[15:8] pinsl0data[7:0] are multiplexed with the data[7:0] pins. if link ports are disabled and are not be used, then these pins can be used as additional data lines for executing instructions at up to the full clock rate from external memory. see data 47:16 on page 15 for more information. lxclk i/o link port clock (link ports 0-1). each lxclk pin has a 50 k ? internal pull-down resistor that is enabled or disabled by the lpdrd bit of the lctl register. lxack i/o link port acknowledge (link ports 0-1). each lxack pin has a 50 k ? internal pull-down resistor that is enabled or disabled by the lpdrd bit of the lcom register. eboot i eprom boot select . for a description of how this pin operates, see the table in the bms pin description. this signal is a system configuration selection that should be hardwired. lboot i link boot . for a description of how this pin operates, see the table in the bms pin description. this signal is a system configuration selection that should be hardwired. bms i/o/t boot memory select . serves as an output or input as selected with the eboot and lboot pins; see table below. this input is a system con- figuration selection that should be hardwired. eboot lboot bms booting mode 1 0 output eprom (connect bms to eprom chip select.) 0 0 1 (input) host processor 0 1 0 (input) serial boot via spi 0 1 1 (input) link port 0 0 0 (input) no booting. processor executes from external memory. 1 1 x (input) reserved for host and prom boot, dma channel 10 (epb0) is used. for link boot and spi boot, dma channel 8 is used. *three-statable only in eprom boot mode (when bms is an output). table 2 pin descriptions (continued) pin type function
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 21 rev. pra clkin i local clock in. used in conjunction with xtal. clkin is the adsp-21161n clock input. it configures the adsp-21161n to use either its internal clock generator or an external clock source. connecting the necessary components to clkin and xtal enables the internal clock generator. connecting the external clock to clkin while leaving xtal unconnected configures the adsp-21161n to use the external clock source such as an external clock oscillator.the adsp-21161n external port cycles at the frequency of clkin. the instruction cycle rate is a multiple of the clkin frequency; it is programmable at power-up via the clk_cfg1-0 pins. clkin may not be halted, changed, or oper- ated below the specified frequency. xtal o crystal oscillator terminal 2. used in conjunction with clkin to enable the adsp-21161n's internal clock generator or to disable it to use an external clock source. see clkin. clk_cfg1-0 i core/clkin ratio control. adsp-21161n core clock (instruction cycle) rate is equal to n x plliclk where n is user selectable to 2, 3, or 4, using the clk_cfg1-0 inputs. these pins can also be used in combina- tion with the clkdbl pin to generate additional core clock rates of 6 x clkin and 8 x clkin ( see table 3- clock rate ratios below). table 2 pin descriptions (continued) pin type function
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 22 rev. pra clkdbl i clock double mode enable. this pin is used to enable the 2x clock dou- ble circuitry, where clkout can be configured as either 1x or 2x the rate of clkin. the 2x clock mode is enabled (during reset low) by tying clkdbl to gnd, otherwise it is connected to vddext for 1x clock mode. this is mainly intended for external crystals to increase exter- nal port clock rate operation. for example, this allows the use of a 25 mhz crystal to enable 100 mhz core clock rates and a 50 mhz external port operation when clk_cfg1='0', clk_cfg1 = '0' and clkdbl = '0'. this pin can also be used to generate different clock rate ratios for external clock oscillators as well. the possible clock rate ratio options (up to 100 mhz) for either clkin (external clock oscillator) or xtal (crys- tal input) are as follows: table 3 clock rate ratios an 8:1 ratio allows the use of a 12.5 mhz crystal to generate a 100 mhz core (instruction clock) rate and a 25 mhz clkout (external port) clock rate. see also figure 8 on page 28 . note: when using an external crystal, the maximum crystal frequency cannot exceed 25 mhz. for all other external clock sources, the maximum clkin frequency is 50 mhz. clkout o/t local clock out. clkout is 1x or 2x and is driven at either 1x or 2x the frequency of clkin frequency by the current bus master. the fre- quency is determined by the clkdbl pin. this output is three-stated when the adsp-21161n is not the bus master or when the host controls the bus (hbg asserted). a keeper latch on the dsp ? s clkout pin maintains the output at the level it was last driven (only enabled on the adsp-21161n with id2-0=00x). if clkdbl enabled, clkout = 2xclkin if cl k dbl disabled, clkout = 1xclkin note: clkout is only controlled by the clkdbl pin and operates at either 1xclkin or 2xclkin. reset i/a processor reset . resets the adsp-21161n to a known state and begins execution at the program memory location specified by the hardware reset vector address. the reset input must be asserted (low) at power-up. table 2 pin descriptions (continued) pin type function clkdbl clk_cfg1 clk_cfg0 core clock ratio ep clock ratio 10 0 2:1 1x 10 1 3:1 1x 11 0 4:1 1x 00 0 4:1 2x 00 1 6:1 2x 01 0 8:1 2x
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 23 rev. pra tck i test clock (jtag) . provides a clock for jtag boundary scan. tms i/s test mode select (jtag) . used to control the test state machine. tms has a 20 k ? internal pull-up resistor. tdi i/s test data input (jtag) . provides serial data for the boundary scan logic. tdi has a 20 k ? internal pull-up resistor. tdo o test data output (jtag) . serial scan output of the boundary scan path. trst i/a test reset (jtag) . resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the adsp-21161n. trst has a 20 k ? internal pull-up resistor. emu o (o/d) emulation status . must be connected to the adsp-21161n analog devices white mountain line of jtag emulators target board connector only. emu has a 50 k ? internal pullup resistor. vddint p core power supply. nominally +1.8 v dc and supplies the dsp ? s core processor (14 pins). vddext p i/o power supply ; nominally +3.3 v dc. (13 pins). avdd p analog power supply ; nominally +1.8 v dc and supplies the dsp ? s internal pll (clock generator). this pin has the same specifications as vddint, except that added filtering circuitry is required. for more information, see ? power supplies ? on page 13. agnd g analog power supply return . gnd g power supply return (26 pins). nc do not connect . reserved pins that must be left open and unconnected. (5 pins). table 2 pin descriptions (continued) pin type function
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 24 rev. pra clock signals the adsp-21161n can use an external clock or a crystal. see clkin pin description. you can configure the adsp-21161n to use its internal clock generator by connecting the necessary components to clkin and xtal. figure 7 shows the component connections used for a crystal operating in fundamental mode. figure 7 100 mhz operation (fundamental mode crystal) target board jtag emulator connector analog devices white mountain line of jtag emulators uses the ieee 1149.1 jtag test access port of the adsp-21161n processor to monitor and control the target board processor during emulation. analog devices white mountain line of jtag emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. the processor's jtag interface ensures that the emulator will not affect target system loading or timing. for complete information on sharc analog devices white mountain line of jtag emulator operation, see the appropriate ? ice tm emulator hardware user's guide ? . for detailed information on the interfacing of analog devices jtag emulators with analog devices dsp products with jtag emulation ports, please refer to engineer to engineer note ee-68, ? analog devices jtag emulation technical reference ? . both of these documents can be found on the analog devices web-site: http://www.analog.com/dsp/tech_docs.html clkin x1 xtal c1 c2 suggested components for 100 ecliptek ec2sm -25.000m c1 = 27pf c2 = 27pf note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. 27pf 27pf this 25mhz crystal generates a 100mhz cclk and 50 mhz ep clock with clkdbl enabled and a 2:1 pll m ultiply ratio. mhz operation: (surface mount package) ecliptek ec-25.000m (thru-hole package) x1
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 25 rev. pra adsp-21161n specifications and timings adsp-21161n-specifications note that component specifications are subject to change without notice. table 4 recommended operating conditions signal k grade parameter min max units v ddint internal (core) supply voltage 1.71 1.89 v av dd analog (pll) supply voltage 1.71 1.89 v v ddext external (i/o) supply voltage 3.13 3.47 v v ih1 high level input voltage 1 , @ vddext = max 1. applies to input and bidirectional pins: data 47-16 , addr 23-0 , ms 3-0 , rd , wr , ack, sbts , irq 2-0 , flag 11-0 , hbg , cs , dmar 1 , dmar 2 , br 6-1 , id 2-0 , rpba, pa , brst, fsx, dxa, dxb, sclkx, ras , cas , sdwe , sdclk 0 , lxdat3-0, lxclk, lx- ack, spiclk, mosi, miso, spids , eboot, lboot, bms , tdo, emu . 2.0 v ddext +0.5 v v ih2 high level input voltage 2 , @ vddext = max 2. applies to input pins: clkin, reset , trst . 2.2 v ddext +0.5 v v il low level input voltage 1,2 , @ vddext = min -0.5 0.8 v t case case operating temperature 3 3. see ? environmental conditions ? on page 72 for information on thermal specifications. 0 +85 c table 5 electrical characteristics parameter test conditions min max units v oh high level output voltage 1 @ v ddext = min, i oh = -2.0 ma 2 2.4 v v ol low level output voltage 1 @ v ddext = min, i ol = 4.0 ma 2 0.4 v i ih high level input current 3,4 @ v ddext = max, v in = v ddext max 10 a i il low level input current 3 @ v ddext = max, v in = 0 v 10 a i ilp low level input current 4 @ v ddext = max, v in = 0 v 150 a i ozh three-state leakage current 5,6,7,8 @ v ddext = max, v in = v ddext max 10 a i ozl three-state leakage current 5,9 @ v ddext = max, v in = 0 v 10 a i ozhp three-state leakage current 9 @ v ddext = max, v in = v ddext max 350 a i ozlar three-state leakage current 8 @ v ddext = max, v in = 0 v 4.2 ma
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 26 rev. pra i ozla three-state leakage current 10 @ v ddext = max, v in = 1.5 v 350 a i ozls three-state leakage current 6 @ v ddext = max, v in = 0 v 150 a i dd- inpeak supply current (internal) 11 t cclk = 10.0 ns, v ddint = max tbd ma i dd- inhigh supply current (internal) 12 t cclk = 10.0 ns, v ddint = max tbd ma i dd- inlow supply current (internal) 13 t cclk = 10.0 ns, v ddint = max tbd ma i dd- idle supply current (idle) 14 v ddint = max tbd ma ai dd supply current (analog) 15 @av dd = max 10 ma c in input capacitance 16,17 f in =1 mhz, t case =25 c, v in =1.8v 4.7 pf 1. applies to output and bidirectional pins: data 47-16 , addr 23-0 , ms 3-0 , r d , wr , ack, flag 11-0 , timexp, hbg , redy, dmag1 , dmag2 , br6-1 , pa , brst, lxdat7-0, lxclk, lxack, spiclk, mosi, miso, b ms , tdo, emu . 2. see ? output drive currents ? on page 67 for typical drive current capabilities. 3. applies to input pins: ack, sbts , irq 2-0 , hbr , cs , dmar 1 , dmar 2 , id2-0, rpba, eboot, spids , lboot, clkin, reset, tck. 4. applies to input pins with internal pull-ups: t rst , tms, tdi. 5. applies to three-statable pins: data 47-16 , addr 24-0 , ms 3-0 , r d , wr , clkout, ack, flag 11-0 , redy, hbg , dmag 1 , dmag 2 , bms , br 6-1 , tdo, emu . (note that ack is pulled up internally with 2 k ? during reset in a multiprocessor system, when id2-0 = 001 and another adsp-21161n is not requesting bus mastership.) 6. applies to three-statable pins with internal pull-ups: dxa, dxb, sclkx, spiclk. 7. applies to pa pin. 8. applies to ack pin when pulled up. (note that ack is pulled up internally with 2 k ? during reset in a multiprocessor system, when id2-0 = 001 and another adsp-21161n is not requesting bus mastership). 9. applies to three-statable pins with internal pull-downs: lxdat7-0, lxclk, lxack. 10.applies to ack pin when keeper latch enabled. 11.the test program used to measure i ddinpeak represents worst case processor operation and is not sustainable under normal application conditions. actual internal power measurements made using typical applications are less than specified. for more information, see ? power dissipation ? on page 67. 12.i ddinhigh is a composite average based on a range of high activity code. for more information, see ? power dissipation ? on page 67. 13.i ddinlow is a composite average based on a range of low activity code. for more information, see ? power dissipation ? on page 67. 14.idle denotes adsp-21161n state during execution of idle instruction. for more information, see ? power dissipation ? on page 67. 15.characterized, but not tested. 16.applies to all signal pins. 17.guaranteed, but not tested. table 5 electrical characteristics (continued) parameter test conditions min max units
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 27 rev. pra esd sensitivity caution: esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000v readily accumulate on the human body and test equipment and can discharge without detection. although the adsp-21161n features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. timing specifications the adsp-21161n ? s internal clock switches at higher frequencies than the system input clock (clkin). to generate the internal clock, the dsp uses an internal phase-locked loop (pll). this pll-based clocking minimizes the skew between the system clock (clkin) signal and the dsp ? s internal clock (the clock source for the external port logic and i/o pads). the adsp-21161n ? s internal clock (a multiple of clkin) provides the clock signal for timing internal memory, processor core, link ports, serial ports, and external port (as required for read/write strobes in asynchronous access mode). during reset, program the ratio between the dsp ? s internal clock frequency and external (clkin) clock frequency with the clk_cfg1-0 and clkdbl pins. even though the internal clock is the clock source for the external port, it is behaves as described on the clock rate ratio chart in clkdbl pin description (see the clkdbl description on page 22 ). to determine switching frequencies for the serial and link ports, divide down the internal clock, using the programmable divider control of each port (divx for the serial ports and lxclkd1-0 for the link ports). note the following definitions of various clock periods that are a function of clkin and the appropriate ratio control. table 6 absolute maximum ratings 1 parameter absolute maximum rating internal (core) supply voltage (v ddint ) -0.3 v to +2.2 v analog (pll) supply voltage (av dd ) -0.3 v to +2.2 v external (i/o) supply voltage (v ddext ) -0.3 v to +4.6 v input voltage -0.5 v to v ddext + 0.5 v tbd output voltage swing -0.5 v to v ddext + 0.5 v tbd load capacitance 200 pf storage temperature range -65 c to +150 c lead temperature (5 seconds) +185 c 1. stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only, and functio nal oper- ation of the device at these or any other conditions greater than those indicated in the operational sections of this specifica tion is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. w arn in g es d s en s itive devic e
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 28 rev. pra figure 8, ? core clock and system clock relationship to clkin ? allows core-to-clkin ratios of 1:1, 2:1, 3:1, 4:1, 6:1, and 8:1 with external oscillator or crystal: figure 8 core clock and system clock relationship to clkin notes: 1. if clkdbl is enabled (tied low at reset), then clkout = plliclk = 2xclkin. otherwise, clk- out = plliclk = clkin. 2. cclk = core clock = plliclk x pll multiply ratio (determined by clk_cfg pins). table 8 clock relationships table 7 adsp-21161n clkout and cclk clock generation operation timing requirements calculation description clkin = 1/t ckin = input clock clkout = 1/t tck = external port system clock plliclk = 1/t pllin = pll input clock cclk = 1/t cclk = core clock timing requirements description 1 t ck = clkout clock period t cclk = (processor) core clock period t lclk = link port clock period = (t cclk ) * lr t sclk = serial port clock period = (t cclk ) * sr t sdk = sdram clock period = (t cclk ) * sdckr t spiclk = spi clock period = (t cclk ) * spir clkin clkdbl clkout (ep system clock rate) 1x/2x input clock doubler 1:1, 2:1 phase-locked loop 2:1, 3:1, 4:1 cclk (core clock) tie to gnd to enable 2x operation plliclk (pll input clock) crystal or clock oscillator
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 29 rev. pra use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. see figure 37 on page 70 under test conditions for voltage reference levels. switching characteristics specify how the processor changes its signals. circuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics describe what the processor will do in a given circumstance. use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. 1. where: lr = link port-to-core clock ratio (1, 2, 3, or 1:4, determined by lxclkd) sr = serial port-to-core clock ratio (wide range, determined by clkdiv) sdckr = sdram-to-core clock ratio (1:1 or 1:2, determined by sdctl register) spir = spi-to-core clock ratio (wide range, determined by spictl register) lclk = link port clock sclk = serial port clock sdk = sdram clock spiclk = spi clock
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 30 rev. pra figure 9 clock input figure 10 reset table 9 clock input parameter 100 mhz min max units timing requirements t ck clkin period 20 tbd ns t ckl clkin width low 8 40 ns t ckh clkin width high 8 40 ns t ckrf clkin rise/fall (0.4v-2.0v) 3 ns table 10 reset parameter min max units timing requirements t wrst reset pulse width low 1 1. applies after the power-up sequence is complete. at power-up, the processor's internal phase-locked loop requires no more tha n100 s while reset is low, assuming stable vdd and clkin (not including start-up time of external clock oscillator). 4t ck ns t srst reset setup before clkin high 2 2. only required if multiple adsp-21161ns must come out of reset synchronous to clkin with program counters (pc) equal. not required for multiple adsp-21161ns communicating over the shared bus (through the external port), because the bus arbitration l ogic synchronizes itself automatically after reset. 7.3 ns clkin t ckh t ck t ckl clkin reset t wrst t srst
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 31 rev. pra figure 11 interrupts timer figure 12 timer table 11 interrupts parameter min max units timing requirements t sir irq 2-0 setup before clkout high 1 1. only required for irq x recognition in the following cycle. 8.3 ns t hir irq 2-0 hold after clkout high 1 -1.6 ns t ipw irq 2-0 pulse width 2 2. applies only if t sir and t hir requirements are not met. 2 + t ck ns table 12 timer parameter min max units switching characteristic t dtex clkout high to timexp -0.9 5.2 ns clkout irq2-0 t ipw t sir t hir clkout tim exp t dtex t dtex
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 32 rev. pra figure 13 flags table 13 flags parameter min max units timing requirement t sfi flag11-0in setup before clkout high 1 6.3 ns t hfi flag11-0in hold after clkout high 1 -0.6 ns t dwrfi flag11-0in delay after rd /wr low 1 tbd ns t hfiwr flag11-0in hold after rd /wr deasserted 1 tbd ns switching characteristics t dfo flag11-0out delay after clkout high 7.2 ns t hfo flag11-0out hold after clkout high -0.9 ns t dfoe clkout high to flag11-0out enable -0.9 ns t dfod clkout high to flag11-0out disable 3.2 ns 1. flag inputs meeting these setup and hold times for instruction cycle n will affect conditional instructions in instruction cy cle n+2. clkout flag11-0 out flag o utput clkout rdx , wrx flag input flag11-0 in t dfo t hfo t dfo t dfod t dfoe t sfi t hfi t hfiwr t dwrfi
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 33 rev. pra memory read--bus master use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to clkout. these specifications apply when the adsp-21161n is the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rd , wr , and dmag strobe timing parameters only apply to asynchronous access mode. table 14 memory read--bus master parameter min max units timing requirements: t dad address, selects delay to data valid 1,2 1. data delay/setup: user must meet t dad , t drld , or t sds. 2. the falling edge of ms x , bms is referenced. t ck ? .25t cclk ? 11+w ns t drld rd low to data valid 1,3 3. note that timing for ack, data, rd , wr , and dmag strobe timing parameters only apply to asynchronous access mode. .75t ck ? 11+w ns t hda data hold from address, selects 4 0ns t sds data setup to rd high 2 ns t hdrh data hold from rd high 3,4 1ns t daak ack delay from address, selects 2,5 t ck ? .5t cclk ? 12+w ns t dsak ack delay from rd low 3,5 t ck ? .75t cclk ? 11+w ns t sakc ack setup to clkout 3,5 .5t cclk +5.3 ns t hakc ack hold after clkout 3 -0.6 ns switching characteristics t drha address selects hold after rd high 3 .25t cclk ? 1+h ns t darl address selects to rd low 2 .25t cclk ? 1ns t rw rd pulse width 3 t ck ? .5t cclk ? 1+w ns t rwr rd high to wr , rd , dmag x low 3 .5t cclk ? 1+hi ns w = (number of wait states specified in wait register) t ck . hi = t ck (if an address hold cycle or bus idle cycle occurs, as specified in wait register; otherwise hi = 0). h = t ck (if an address hold cycle occurs as specified in wait register; otherwise h = 0).
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 34 rev. pra figure 14 memory read--bus master 4. data hold: user must meet t hda or t hdrh in asynchronous access mode. see ? example system hold time calculation ? on page 69 for the calculation of hold times given capacitive and dc loads. 5. ack delay/setup: user must meet t daak , t dsak , or t sakc for deassertion of ack (low), all three specifications must be met for as- sertion of ack (high). wr , dmag ack data rd address ms x, bms t darl t rw t dad t daak t hdrh t hda t rwr t drld t drha t dsak t sds t sakc t hakc clkout
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 35 rev. pra memory write--bus master use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to clkout. these specifications apply when the adsp-21161n is the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rd , wr , and dmag strobe timing parameters only apply to asynchronous access mode. table 15 memory write--bus master parameter min max units timing requirements t daak ack delay from address, selects 1,2 t ck ? .5t cclk ? 12+w ns t dsak ack delay from wr low 1,3 t ck ? .75t cclk ? 11+w ns t sakc ack setup to clkout 1,3 .5t cclk +5.3 ns t hakc ack hold after clkout 1,3 -0.6 ns switching characteristics t dawh address selects to wr deasserted 2,3 t ck ? .25t cclk ? 2+w ns t dawl address selects to wr low 2 .25t cclk ? 2ns t ww wr pulse width 3 t ck ? .5t cclk ? 1+w ns t ddwh data setup before wr high 3 t ck ? .25t cclk ? 12.5+w ns t dwha address hold after wr deasserted 3 .25t cclk ? 1+h ns t dwhd data hold after wr deasserted 3 .25t cclk ? 1+h ns t datrwh data disable after wr deasserted 3,4 .25t cclk ? 1+h .25t cclk +2+h ns t wwr wr high to wr , rd , dmagx low 3 .5t cclk ? 1+hi ns t ddwr data disable before wr or rd low .25t cclk ? 1+i ns t wde wr low to data enabled ? .25t cclk ? 1ns
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 36 rev. pra figure 15 memory write--bus master w = (number of wait states specified in wait register) t ck . h = t ck (if an address hold cycle occurs, as specified in wait register; otherwise h = 0). hi = t ck (if an address hold cycle or bus idle cycle occurs, as specified in wait register; otherwise hi = 0). i = t ck (if a bus idle cycle occurs, as specified in wait register; otherwise i = 0). 1. ack delay/setup: user must meet t daak or t dsak or t sakc for deassertion of ack (low), all three specifications must be met for assertion of ack (high). 2. the falling edge of ms x , bms is referenced. 3. note that timing for ack, data, rd , wr , and dmag strobe timing parameters only apply to asynchronous access mode. 4. see ? example system hold time calculation ? on page 69 for calculation of hold times given capacitive and dc loads. table 15 memory write--bus master parameter min max units t datrwh rd , dmag ack data wr address ms x , bms t dawl t ww t daak t wwr t wde t ddwr t dwha t dawh t dsak t ddwh t dwhd t sakc t hakc clkout
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 37 rev. pra synchronous read/write--bus master use these specifications for interfacing to external memory systems that require clkout, relative to timing or for accessing a slave adsp-21161n (in multiprocessor memory space). these synchronous switching characteristics are also valid during asynchronous memory reads and writes except where noted (see ? memory read--bus master ? on page 33 and ? memory write--bus master ? on page 35 ). when accessing a slave adsp-21161n, these switching characteristics must meet the slave's timing requirements for synchronous read/writes (see ? synchronous read/write--bus slave ? on page 39 ). the slave adsp-21161n must also meet these (bus master) timing requirements for data and acknowledge setup and hold times. table 16 synchronous read/write--bus master parameter min max units timing requirements t ssdati data setup before clkout n 1 1. note that timing for ack, data, rd , wr , and dmag strobe timing parameters only applies to synchronous access mode. 6.8 ns t hsdati data hold after clkout n 1 -0.6 ns t sackc ack setup before clkout n 1 .5t cclk +5.3 ns t hackc ack hold after clkout n 1 -0.6 ns switching characteristics t daddo address, ms x, bms , brst, delay after clkin 8.2 ns t haddo address, ms x, bms , brst, hold after clkin -0.4 ns t drdo rd high delay after clkout n 1 .25t cclk ? 2.9 .25t cclk +7.2 ns t dwro wr high delay after clkout n 1 .25t cclk ? 2.9 .25t cclk +7.2 ns t drwl rd /wr low delay after clkout .25t cclk ? 2.9 .25t cclk +7.2 ns t ddato data delay after clkout 10.7 ns t hdato data hold after clkout -0.4 ns t dackmo ack delay after clkout n 2 2. applies to broadcast write, master precharge of ack. .25t cclk +1.1 .25t cclk +7.2 ns t ackmtr ack disable before clkout n 2 .25t cclk ? 4.9 ns t dckoo clkout delay after clkin 1.6 2.3 ns t ckop clkout period t ck t ck 3 3. applies only when the dsp drives a bus operation; clkout held inactive or three-state otherwise, for more information, see th e system design chapter in the adsp-21160 or adsp-21161n sharc dsp technical reference. ns t ckwh clkout width high t ck /2 - 2 t ck /2 + 2 3 ns t ckwl clkout width low t ck /2 - 2 t ck /2 + 2 3 ns
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 38 rev. pra figure 16 synchronous read/write--bus master t dckoo t ckop t ckwl t ckwh clkin clkout address ms x, brst t haddo t daddo ack (in) rd data (out) wr data (in) write cycle read cycle t drwl t hsdati t ssdati t drdo t dwro t hdato t ddato t drwl t sackc t hackc ack (out) t dackmo t ackmtr
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 39 rev. pra synchronous read/write--bus slave use these specifications for adsp-21161n bus master accesses of a slave's iop registers in multiprocessor memory space. the bus master must meet these (bus slave) timing requirements. table 17 synchronous read/write--bus slave parameter min max units timing requirements: t saddi address, brst setup before clkout 7.3 ns t haddi address, brst hold after clkout -0.6 ns t srwi rd /wr setup before clkout 7.3 ns t hrwi rd /wr hold after clkout -0.6 ns t ssdati data setup before clkout 6.8 ns t hsdati data hold after clkout -0.6 ns switching characteristics t ddato data delay after clkout 10.7 ns t hdato data hold after clkout -0.4 ns t dackc ack delay after clkout 8.2 ns t hacko ack hold after clkout -0.4 ns
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 40 rev. pra figure 17 synchronous read/write--bus slave clkout address ack rd data (out) wr write access data (in) read access t saddi t haddi t dackc t hacko t hrwi t srwi t ddato t hdato t srwi t hrwi t hsdati t ssdati
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 41 rev. pra multiprocessor bus request and host bus request use these specifications for passing of bus mastership between multiprocessing adsp-21161ns (brx ) or a host processor (hbr , hbg ). table 18 multiprocessor bus request and host bus request parameter min max units timing requirements: t hbgrcsv hbg low to rd /wr /cs valid 1 tbd tbd ns t shbri hbr setup before clkout n 2 8.3 ns t hhbri hbr hold after clkout n 2 -0.6 ns t shbgi hbg setup before clkout n 8.3 ns t hhbgi hbg hold after clkout high -0.6 ns t sbri br x , pa setup before clkout n 11.3 ns t hbri br x , pa hold after clkout high -0.6 ns t spai pa setup before clkout n 11.3 ns t hpai pa hold after clkout high -0.6 ns t srpbai rpba setup before clkout n 8.3 ns t hrpbai rpba hold after clkout n 0.4 ns switching characteristics t dhbgo hbg delay after clkout tbd ns t hhbgo hbg hold after clkout tbd ns t dbro brx delay after clkout 7.2 ns t hbro br x hold after clkout -0.4 ns t dpaso pa delay after clkout, slave 7.2 ns t trpas pa disable after clkout, slave -0.4 ns t dpamo pa delay after clkout, master .25t cclk +7.2 ns t patr pa disable before clkout, master .25t cclk +0.6 ns t drdycs redy (o/d) or (a/d) low from cs and hbr low 3 tbd ns t trdyhg redy (o/d) disable or redy (a/d) high from hbg 3 tbd ns see note on page 42 .
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 42 rev. pra t ardytr redy (a/d) disable from cs or hbr high 3 tbd ns 1. for first asynchronous access after hbr and cs asserted, addr 23-0 must be a non-mms value (tbd) before rd or wr goes low or by t hbgrcsv after hbg goes low. this is easily accomplished by driving an upper address signal high when hbg is asserted. 2. only required for recognition in the current cycle. 3. (o/d) = open drain, (a/d) = active drive. table 18 multiprocessor bus request and host bus request parameter min max units see note on page 42 .
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 43 rev. pra figure 18 multiprocessor bus request and host bus request br x (in) t hbri hbr cs rpba redy (o/d) redy (a/d) hbg (out) rd wr cs o/d = open drain, a/d = active drive t hrpbai t srpbai t drdycs t hbgrcsv t trdyhg t ardytr hbg (in) t shbgi t hhbgi t sbri clkout hbr hbg (out) br x (out) pa (out) (slave) t hhbri t shbri t hhbgo t dhbgo t dbro t hbro t dpaso t trpas pa (out) (master) t dpamo t patr pa (in) (o/d) t hpai t spai
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 44 rev. pra asynchronous read/write--host to adsp-21161n use these specifications (continued on page 45 and page 46 ) for asynchronous host processor accesses of an adsp-21161n, after the host has asserted cs and hbr (low). after hbg is returned by the adsp-21161n, the host can drive the rd and wr pins to access the adsp-21161n's iop register. hbr and hbg are assumed low for this timing. note: host internal memory access is not supported. figure 19 synchronous redy timing table 19 write cycle (synchronous redy) parameter min max units switching characteristics t srdyck redy (o/d) or (a/d) disable to clkout tbd tbd ns clkiout redy (o/d) o/d = open drain, a/d = active drive t srdyck redy (a/d)
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 45 rev. pra table 20 read cycle parameter min max units timing requirements t sadrdl address setup cs low before rd low 1 0ns t hadrdh address hold cs hold low after rd 0ns t wrwh rd /wr high width 5 ns t drdhrdy rd high delay after redy (o/d) disable 0 ns t drdhrdy rd high delay after redy (a/d) disable 0 ns switching characteristics t sdatrdy data valid before redy disable from low 2 ns t drdyrdl redy (o/d) or (a/d) low delay after rd low 10 ns t rdyprd redy (o/d) or (a/d) low pulse width for read 2t ck ns t hdarwh data disable after rd high 2 tbd ns 1. not required if rd and address are valid t hbgrcsv after hbg goes low. for first access after hbr asserted, addr 23-0 must be a non-mms value (tbd) before rd or wr goes low or by t hbgrcsv after hbg goes low. this is easily accomplished by driving an upper address signal high when hbg is asserted. redy (o/d) rd read cycle address/ cs data (out) redy (a/d) t sadrdl t drdyrdl t wrwh t hadrdh t hdarwh t rdyprd t drdhrdy t sdatrdy figure 20 asynchronous read--host to adsp-21161n
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 46 rev. pra table 21 write cycle parameter min max units timing requirements t scswrl cs low setup before wr low 0 ns t hcswrh cs low hold after wr high 0 ns t sadwrh address setup before wr high 5 ns t hadwrh address hold after wr high 2 ns t wwrl wr low width 7 ns t wrwh rd /wr high width 5 ns t dwrhrdy wr high delay after redy (o/d) or (a/d) disable 0 ns t sdatwh data setup before wr high 5 ns t hdatwh data hold after wr high 1 ns switching characteristics t drdywrl redy (o/d) or (a/d) low delay after wr /cs low 10 ns t rdypwr redy (o/d) or (a/d) low pulse width for write tbd ns o/d = open drain, a/d = active drive redy (o/d) wr write cycle data (in) address redy (a/d) cs t sdatwh t hdatwh t wwrl t drdywrl t wrwh t hadwrh t rdypwr t dwrhrdy t sadwrh t scswrl t hcswrh figure 21 asynchronous write--host to adsp-21161n
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 47 rev. pra three-state timing--bus master, bus slave, hbr, sbts these specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to clkout and the sbts pin. this timing is applicable to bus master transition cycles (btc) and host transition cycles (htc) as well as the sbts pin. table 22 three-state timing--bus slave, hbr , sbts parameter min max units timing requirements t stsck sbts setup before clkout 8.3 ns t htsck sbts hold after clkout -0.6 ns switching characteristics t miena address/select enable after clkout -0.4 7.2 ns t miens strobes enable after clkout 1 1. strobes = rd , wr , dmag x. -0.4 3.2 ns t mienhg hbg enable after clkout -0.4 7.2 ns t mitra address/select disable after clkout .5t ck -0.9 .5t ck +3.2 ns t mitrs strobes disable after clkout 1 t ck ? .25t cclk -1.9 t ck ? .25t cclk +3.2 ns t mitrhg hbg disable after clkout -0.4 3.2 ns t daten data enable after clkout n 2 2. in addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write. -0.4 7.2 ns t dattr data disable after clkout 2 -0.4 3.2 ns t acken ack enable after clkout 2 -0.4 7.2 ns t acktr ack disable after clkout 2 1.5 5 ns t cdcen clkout enable after clkin -0.4 7.2 ns t cdctr clkout disable after clkin .5t ck -0.9 .5t ck +3.2 ns t mtrhbg memory interface disable before hbg low 3 3. memory interface = address, rd , wr , msx , d mag x , bms (in eprom boot mode). .5t ck ? 4tbd ns t menhbg memory interface enable after hbg high 3 t ck ? 5tbdns
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 48 rev. pra figure 22 three-state timing dma handshake these specifications describe the three dma handshake modes. in all three modes dmar is used to initiate transfers. for handshake mode, dmag controls the latching or enabling of data externally. for external handshake mode, the data transfer is controlled by the addr 24-0 , rd , wr , m s 3-0 , ack, and dmag signals. for paced master mode, the data transfer is controlled by addr 24-0 , rd , wr , ms 3-0 , and ack (not dmag ). for paced master mode, the memory read-bus master, memory write-bus master, and synchronous read/write-bus master timing specifications for addr 23-0 , rd , wr , ms3-0 , data 47-16 , and ack also apply. table 23 dma handshake parameter min max units timing requirements t sdrc dmarx setup before clkout n 1 5.3 ns t wdr dmarx width low (nonsynchronous) .5t ck +1 ns t sdatdgl data setup after dmagx low 2 .75t ck ? 7ns t hdatidg data hold after dmagx high 2 ns clkout sbts ack memory in te r fa c e t m trhbg hbg m em o ry interface = address, rd , wr , ms x, hbg , dmag x. bms (in eprom boot mode) clkout t menhbg t cdctr data memory in te r fa c e t mitra , t mitrs , t mitrhg t stsc k t htsck t dattr t daten t acktr t acken t cdcen t miena , t miens , t mienhg clkin
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 49 rev. pra t datdrh data valid after dmar x high 2 tbd ns t dmarll dmar x low edge to low edge 3 t ck ns t dmarh dmar x width high .5t ck +1 ns switching characteristics t ddgl dmag x low delay after clkout .25t cclk -0.9 .25t cclk +7.2 ns t wdgh dmag x high width .5t cclk ? 1+hi ns t wdgl dmag x low width t ck ? .5t cclk ? 1ns t hdgc dmag x high delay after clkout t ck ? .25t cclk -0.4 t ck ? .25t cclk +7.2 ns t vdatdgh data valid before dmag x high 4 t ck ? .25t cclk ? 8t ck ? .25t cclk +5 ns t datrdgh data disable after dmag x high 5 .25t cclk +1.5 .25t cclk +1.5 ns t dgwrl wr low before dmag x low ? 11 ns t dgwrh dmag x low before wr high t ck ? .5t cclk ? 2+w ns t dgwrr wr high before dmag x high 6 ? 11 ns t dgrdl rd low before dmag x low ? 11 ns t drdgh rd low before dmag x high t ck ? .5t cclk ? 2+w ns t dgrdr rd high before dmag x high 6 ? 11 ns t dgwr dmar x high to wr , rd , dmag x low .5t cclk ? 1+hi ns t dadgh address/select valid to dmag x high tbd ns t ddgha address/select hold after dmag x high tbd ns w = (number of wait states specified in wait register) t ck . hi = t ck (if data bus idle cycle occurs, as specified in wait register; otherwise hi = 0). 1. only required for recognition in the current cycle. 2. t sdatdgl is the data setup requirement if dmar x is not being used to hold off completion of a write. otherwise, if dmar x low holds off completion of the write, the data can be driven t datdrh after dmar x is brought high. table 23 dma handshake (continued) parameter min max units
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 50 rev. pra figure 23 dma handshake timing 3. use t dmarll if dmar x transitions synchronous with clkout. otherwise, use t wdr and t dmarh . 4. t vdatdgh is valid if dmar x is not being used to hold off completion of a read. if dmar x is used to prolong the read, then t vdatdgh =t ck ? .25t cclk ? 8+(n t ck ) where n equals the number of extra cycles that the access is prolonged. 5. see ? example system hold time calculation ? on page 69 for calculation of hold times given capacitive and dc loads. 6. this parameter applies for synchronous access mode only. clkout t sdrc dmarx data data rd wr t wdr t sdrc t dmarh t dmarll t hdgc t wdgh t ddgl dmagx t vdatdgh t datdrh t datrdgh t hdatidg t dgwrl t dgwrh t dgwrr t dgrdl t drdgh t dgrdr t sdatdg l * memory read bus master, memory write bus master, or synchronous read/write bus master tim ing specifications for addr 23-0 , rd , wr , ms 3-0 and ack also apply here. (external device to external m em o ry) (external memory to external device) transfers between adsp-21161n internal memory and external device transfers between external device and external memory* (external handshake mode) t ddgha address msx , t dadgh t wdgl (from external drive to adsp-21161n) (from adsp-2116x to external drive)
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 51 rev. pra sdram interface ? bus master use these specifications for adsp-21161n bus master accesses of sdram: parameter min max units timing requirements: t sdsdk data setup before sdclk 2.0 ns t hdsdk data hold after sdclk 1.5 ns switching characteristics: t dsdk1 first sdclk rise delay after clkout 1, 2 1. for the second, third, and forth rising edges of sdclk delay from clkout, add appropriate number of sdclk period to the t dsdk1 and t ssdkc1 values, depending upon the sdckr value and the core clk to clkout ratio. 2. sdckr = 1 for sdclk equal to core clock frequency and sdckr = 2 for sdclk equal to half core clock frequency. 3.command = sdcke, ras , cas , and sdwe . 4. sdram controller adds one sdram clk three-stated cycle delay on a read followed, by a write. sdckr x t cclk -0.25 x t cclk - 0.4 sdckr x t cclk -0.25 x t cclk + 1.7 ns t sdk sdclk period 10.0 2 x t cclk ns t sdkh sdclk width high 4.0 ns t sdkl sdclk width low 4.0 ns t dcadsdk command, address, data, delay after sdclk 3 .25 x t cclk + 2.0 ns t hcadsdk command, address, data, hold after sdclk 3 1.3 ns t sdtrsdk data three-state after sdclk 0.5 x t cclk + 2.0 ns t sdensdk data enable after sdclk 4 0.75 x t cclk ns t sdctr command three-state after clkout 3 0.5 x t cclk - 0.4 0.5 x t cclk + 1.7 ns t sdcen command enable a fter clkout 3 -0.4 1.7 ns t sdsdktr sdclk three-state after clkout -0.4 1.7 ns t sdsdken sdclk enable after clkout -0.4 1.7 ns t sdatr address three-state after clkout 0.5 x t ck - 0.9 0.5 x t ck + 3.2 ns t sdaen address enable after clkout -0.4 7.2 ns
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 52 rev. pra sdram interface ? bus slave these timing requirements allow a bus slave to sample the bus master ? s sdram command and detect when a refresh occurs. notes 1. for the second, third, and forth rising edges of sdclk delay from clkout, add appropriate number of sdclk period to the t dsdk1 and t ssdkc1 values, depending upon the sdckr value and the core clk to clkout ratio. 2. sdckr = 1 for sdclk equal to core clock frequency and sdckr = 2 for sdclk equal to half core clock frequency. 3.command = sdcke, ras , cas , and sdwe . parameter min max unit timing requirements: t ssdkc1 first sdclk rise after clkout 1, 2 sdckr x tcclk -0.5 x t cclk -1.4 sdckr x tcclk -0.25 x t cclk + 2.7 ns t scsdk command setup before sdclk 3 0.0 ns t hcsdk command hold after sdclk 3 2.0 ns
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 53 rev. pra figure 24 sdram interface t hcsdk t scsdk t ssdkc1 t sdaen t sd atr t sdc tr t hcadsdk t hcadsdk t sdtrsdk t dcadsdk t sdcen t sdsdk t dcadsdk t sdensdk t hdsdk t sdkl t sdkh t sdk clkout sdclk data (in) data (out) cmnd 1 addr (out) cmnd 1 (out) addr (out) sdclk (in) cmnd 2 (in) clkout notes 1 command = sdcke, ms x , ras, cas, sdwe, dqm and sda10. 2 sdram controller adds one sdram clk three-stated cycle delay on a read followed by a write.
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 54 rev. pra link ports calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path between ldata and lclk. setup skew is the maximum delay that can be introduced in ldata relative to lclk, (setup skew = t lclktwh min ? t dldch ? t sldcl ). hold skew is the maximum delay that can be introduced in lclk relative to ldata, (hold skew = t lclktwl min ? t hldch ? t hldcl ). calculations made directly from speed specifications will result in unrealistically small skew times because they include multiple tester guardbands. the setup and hold skew times shown below are calculated to include only one tester guardband. adsp-21161n setup skew = tbd ns max adsp-21161n hold skew = tbd ns max note that there is a two-cycle effect latency between the link port enable instruction and the dsp enabling the link port. figure 25 link ports ? receive table 24 link ports receive parameter min max units timing requirements t sldcl data setup before lclk low 2 ns t hldcl data hold after lclk low 2 ns t lclkiw lclk period t lclk ns t lclkrwl lclk width low 3.5 ns t lclkrwh lclk width high 3.5 ns switching characteristics t dlalc lack low delay after lclk high 1 1. lack goes low with t dlalc relative to rise of lclk after first nibble, but doesn ? t go low if the receiver's link buffer is not about to fill. tbd tbd ns lclk ldat(7:0) lack (out) receive in t sldcl t hldcl t lclkrwh t dlalc t lclkrwl t lclkiw
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 55 rev. pra figure 26 link ports ? transmit table 25 link ports transmit parameter min max units timing requirements t slach lack setup before lclk high 15 ns t hlach lack hold after lclk high ? 2ns switching characteristics t dldch data delay after lclk high 2 ns t hldch data hold after lclk high ? 2ns t lclktwl lclk width low .5t lclk ? 1 .5t lclk +1 ns t lclktwh lclk width high .5t lclk ? 1 .5t lclk +1 ns t dlaclk lclk low delay after lack high .5t lclk +5 3t lclk +11 ns lclk ldat(7:0) lack (in) the t slach req uirem ent applies to the rising edg e o f lclk only fo r the first nibble transm itted. transmit last nibble/byte transm itted first nibble/byte transm itted lclk inactive (hig h) out t dldch t hldch t lclktwh t lclktwl t slach t hlach t dlaclk
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 56 rev. pra serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay & frame sync setup and hold, 2) data delay & data setup and hold, and 3) sclk width. table 26 serial ports ? external clock parameter min max units timing requirements t sfse transmit/receive fs setup before trans- mit/receive sclk 1 1. referenced to sample edge. 3.5 ns t hfse transmit/receive fs hold after trans- mit/receive sclk 1, 2 2. fsx hold after receive sclk when mce = 1, mfd = 0 is 0 ns minimum from drive edge. transmit fs hold after transmit sclk for late external transmit fs is 0 ns minimum from drive edge. 4ns t sdre receive data setup before receive sclk 1, 3 3. sclk/fs configured as a receive clock/frame sync with the ddir bit = 0 in spctlx register. 1.5 ns t hdre receive data hold after sclk 1, 4 4. sclk/fs configured as a transmit clock/frame sync with the ddir bit = 1 in spctlx register. 4ns t sclkw sclkx width 9 ns t sclk sclkx period 2t cclk ns table 27 serial ports ? internal clock parameter min max units timing requirements t sfsi fs setup time before sclk 1 , 2 1. referenced to sample edge. 2. sclk/fs configured as a receive clock/frame sync with the ddir bit = 0 in spctlx register. 8ns t hfsi fs hold after sclk 1, 2, 3 3. fsx hold after receive sclk when mce = 1, mfd = 0 is 0 ns minimum from drive edge. transmit fs hold after transmit sclk for late external transmit fs is 0 ns minimum from drive edge. 1ns t sdri receive data setup before sclk 1 3ns t hdri receive data hold after sclk 1 3ns
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 57 rev. pra table 28 serial ports ? external or internal clock parameter min max units switching characteristics t dfse fs delay after sclk ( 1 ) (internally generated fs) 2 1. sclk/fs configured as a receive clock/frame sync with the ddir bit = 0 in spctlx register. 2. referenced to drive edge. 13 ns t hofse fs hold after receive sclk ( 1 ) (internally gen- erated fs) 1 3ns table 29 serial ports ? external clock parameter min max units switching characteristics t dfse fs delay after transmit sclk (internally gen- erated transmit fs) 1 , 2 1. referenced to drive edge. 2. sclk/fs configured as a transmit clock/frame sync with the ddir bit = 1 in spctlx register. 13 ns t hofse fs hold after transmit sclk (internally gener- ated transmit fs 1, 2 3ns t ddte transmit data delay after transmit slck 1, 2 16 ns t hodte transmit data hold after transmit sclk 1, 2 0ns table 30 serial ports ? internal clock parameter min max units switching characteristics t dfsi transmit fs delay after sclk (internally gen- erated transmit fs) 1 , 2 4.5 ns t hofsi transmit fs hold after sclk (internally gener- ated transmit fs) 1, 2 -1.5 ns
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 58 rev. pra t ddti transmit data delay after sclk 1, 2 7.5 ns t hdti transmit data hold after sclk 1, 2 0ns t sclkiw transmit or receive sclk width 2 .5t sclk ? 2.5 .5t sclk +2 ns 1. referenced to drive edge. 2. sclk/fs configured as a transmit clock/frame sync with the ddir bit = 1 in spctlx register. table 31 serial ports ? enable and three-state parameter min max units switching characteristics t ddten data enable from external transmit sclk 1 , 2 1. referenced to drive edge. 2. sclk/fs configured as a transmit clock/frame sync with the ddir bit = 1 in spctlx register. 4ns t ddtte data disable from external transmit sclk 1 10 ns t ddtin data enable from internal transmit sclk 1 0ns t ddtti data disable from internal transmit sclk 1 3ns table 32 serial ports ? external late frame sync parameter min max units switching characteristics t ddtlfse data delay from late external transmit fs or external receive fs with mce = 1, mfd = 0 1 1. mce = 1, transmit fs enable and transmit fs valid follow t ddtlfse and t ddtenfs . 13 ns t ddtenfs data enable from late fs or mce = 1, mfd = 0 1 3.5 ns table 30 serial ports ? internal clock parameter min max units
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 59 rev. pra figure 27 serial ports drive edge drive edge drive edge drive edge sclk sclk (int) sclk sclk (ext) t ddtte t ddten t ddtti t ddtin sclk fs drive edge sample edge d a ta rec eiv e? in tern a l c lo c k data receive? external clock sclk fs drive edge sample edge note: either the rising edge or falling edge of sclk (external), sclk (internal) can be used as the active sampling edge. t sdri t hdri t sfsi t hfsi t dfse t hofse t sclkiw t sdre t hdre t sfse t hfse t dfse t sclkw t hofse dxa/dxb dxa/dxb dxa/dxb dxa/dxb
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 60 rev. pra figure 28 external late frame sync (see note 2) drive sample drive sclk fs dxa/dxb drive sample drive late external transmit fs external receive fs with mce = 1, mfd = 0 1st bit 2nd bit sclk fs 1st bit 2nd bit (see note 2) t hofse/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i t hofse/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i dxa/dxb
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 61 rev. pra spi interface specifications table 33 spi interface protocol ? timing specifications name parameter mode min max units t spiclk minimum serial clock cycle master tbd ns t spichm serial clock high period master tbd ns t spichs serial clock low period slave tbd ns t spiclm serial clock low period master tbd ns t spicls serial clock high period slave tbd ns t sdsco s pids assertion to first spiclk edge cphase=0 cphase=1 t sdsci cp0=1 slave slave tbd tbd ns t hds last spiclk edge to spids not asserted slave tbd ns t sspid data input valid to spiclk edge (data input set-up time) master/ slave tbd ns t hspid spiclk last sampling edge to data input not valid master/ slave tbd ns t dsoe ( t spidsoe) spids assertion to data out active slave tbd ns t dsdhi spids deassertion to data high impedance slave tbd ns t ddspid spiclk edge to data out valid (data out delay time) master/ slave tbd ns t hdspid spiclk edge to data out not valid (data out hold time) master/ slave tbd ns t dsov spids assertion to data out valid (cphase=0) slave tbd ns t sdppw spids deassertion pulse width (cphase=0) slave tbd ns
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 62 rev. pra figure 29 spi master timing (cpha=0) figure 30 spi slave timing (cpha=0) tspiclk tspiclk spids (input) miso (input) va lid mosi ms b valid ls b ms b ls b tspichs tspiclk spiclk (cpol = 1 (output) tspichs tspicls tspicls tspiclk thspid tsspid tsspid thspid thdspid tddspid spiclk (cpol = 0 (output)
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 63 rev. pra figure 31 spi master timing (cpha=1) spids (input) miso (input) valid msb valid lsb ms b lsb spiclk (cpol = 0 (output) spiclk (cpol = 1 (output) thspid tspichm tspiclm tspiclm tspichm tspiclk thdspid tsspid thspid tddspid tsspid mosi (output) tspiclk
july 2000 adsp-21161n preliminary data sheet for current information contact analog devices at (781) 461-3881 this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 64 rev. pra figure 32 spi slave timing (cpha=0) msb valid spids (input) miso (ouput) tspiclk tspicls tspichs spiclk (cpol = 0) tspicls tspichs tdsoe tddspid thspid thspid tsspid tsspi d thspid tspidsoe tsdsci tdsov thds tsdppw tspiclk (input) spiclk (cpol = 1) (input) (input) mosi msb valid lsb valid lsb valid
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 65 rev. pra figure 33 spi slave timing (cpha=1) spids (input) miso (output) mosi (input) msb lsb msb lsb valid valid sclk (cpol = 0) (input) sclk (cpol = 1) (input) tspicls tspichs tspiclk tsdsci thds tsspid tsspid thspid thspid tdsoe tdsdhi tddspid tspichs tspicls tdsdhi tspidsoe
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 66 rev. pra figure 34 ieee 11499.1 jtag test access port table 34 jtag test access port and emulation parameter min max units timing requirements t tck tck period t ck ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys system inputs setup before tck low 1 7ns t hsys system inputs hold after tck low 1 18 ns t trstw trst pulse width 4t ck ns switching characteristics t dtdo tdo delay from tck low 13 ns t dsys system outputs delay after tck low 2 18 ns 1. system inputs = data 47-16 , addr 23-0 , rd , wr , ack, rpba, spids , eboot, lboot, dmar 2-1, clk_cfg 1-0 , clkdbl , cs , hbr , sbts , id 2-0 , irq 2-0 , reset , bms , miso, mosi, spiclk, dxa, dxb, sclkx, fsx, lxdat 7-0 , lxclk, lxack, sdwe , hbg , ras , cas , sdclk0, sdcke, brst, br 6-1 , pa , ms 3-0 , flag 11-0 2. system outputs = bms , miso, mosi, spiclk, dxa, dxb, sclkx, fsx, lxdat 7-0 , lxclk, lxack, data 47-16 , sdwe , ack, hbg , ras , cas , sdclk 1-0 , sdcke, brst, rd , wr , br 6-1 , pa , ms 3-0 , addr 23-0 , flag 11-0 , dmag 2-1 , dqm, redy, clkout, sda10, timexp, emu , bmstr . tck tm s tdi tdo system inputs system outputs t stap t tck t htap t dtdo t ssys t hsys t dsys
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 67 rev. pra output drive currents figure 38 on page 70 shows typical i-v characteristics for the output drivers of the adsp-21161n. the curves represent the current drive capability of the output drivers as a function of output voltage. power dissipation total power dissipation has two components: one due to internal circuitry and one due to the switching of external output drivers. internal power dissipation is dependent on the instruction execution sequence and the data operands involved. using the current specifications (i ddinpeak , i ddinhigh , i ddinlow , i ddidle ) from table 5 on page 25 and the current-versus-operation information in table 35 , you can estimate the adsp-21161n ? s internal power supply (v ddint ) input current for a specific application, according to the following formula: %peak i ddinpeak %high i ddinhigh %low i ddinlow +%idle i ddidle i ddint the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: the number of output pins that switch during each cycle (o) the maximum frequency at which they can switch (f) table 35 adsp-21161n operation types versus input current operation peak activity 1 (i ddinpeak ) 1. the state of the peyen bit (simd versus sisd mode) does not influence these calculations. high activity 1 (i ddinhigh ) low activity 1 (i ddinlow ) instruction type multifunction multifunction single function instruction fetch cache internal memory internal memory core memory access 2 2. these assume a 2:1 core clock ratio. for more information on ratios and clocks (t ck and t cclk ), see the timing ratio definitions on page 27 . 2 per t ck cycle (dm 64 and pm 64 ) 1 per t ck cycle (dm 64 ) none internal memory dma 1 per 2 t cclk cycles 1 per 2 t cclk cycles n/a external memory dma 1 per external port cycle ( 32) 1 per external port cycle ( 32) n/a data bit pattern for core memory access and dma worst case random n/a
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 68 rev. pra their load capacitance (c) their voltage swing (vdd) and is calculated by: pext = o c vdd 2 f the load capacitance should include the processors package capacitance (cin). the switching frequency includes driving the load high and then back low. address and data pins can drive high and low at a maximum rate of 1 tck while writing to a sddram memory. example: estimate pext with the following assumptions: a system with one bank of external memory (32 bit) two 1m x 16 sdram chips are used, each with a load of 10pf external data memory writes can occur every cycle at a rate of 1/tck, with 50% of the pins switch- ing the bus cycle time is 50mhz the external sdram clock rate is 100mhz the pext equation is calculated for each class of pins that can drive: a typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: p total = p ext + p int + p pll where: p ext is from table 36 p int is i ddint 1.8v, using the calculation i ddint listed in ? power dissipation ? on page 67 p pll is ai dd 1.8v, using the value for ai dd listed in table 5 on page 25 note that the conditions causing a worst-case pext are different from those causing a worst-case pint. maximum pint cannot occur while 100% of the output pins are switching from all ones to all table 36 external power calculations (3.3 v device) pin type # of pins % switching c f vdd 2 = p ext address 11 50 44.7 pf 50 mhz 10.9 v = 0.134 w msx 4 0 44.7 pf - 10.9 v = 0.000 w sdwe 11 44.7 pf - 10.9 v = 0.024 w data 32 50 14.7 pf 50 mhz 10.9 v = 0.128 w sdclk0 1 - 10.7 pf 100 mhz 10.9 v = 0.012 w p ext = 0.298 w
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 69 rev. pra zeros. note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. test conditions output disable time output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by ? v is dependent on the capacitive load, cl and the load current, il. this decay time can be approximated by the following equation: t decay = (c l ? v)/i l the output disable time t dis is the difference between t measured and t decay as shown in figure 25. the time t measured is the interval from when the reference signal switches to when the output voltage decays ? v from the measured output high or output low voltage. t decay is calculated with test loads cl and il, and with ? v equal to 0.5 v. output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram ( figure 35 ). if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose ? v to be the difference between the adsp-21161n's output voltage and the input threshold for the device requiring the hold time. a typical ? v will be 0.4 v. cl is the total bus capacitance (per data line), and il is the total leakage or three-state current (per data line). the hold time will be t decay plus the minimum disable time (i.e., t datrwh for the write cycle). figure 35 output enable/disable reference signal t dis output starts driving v oh (measured) - dv v ol (measured) + dv t measured v oh (measured) v ol (measured) 2.0v 1.0v v oh (measured) v ol (measured) high-impedance state. test conditions cause this voltage to be approximately 1.5v output stops driving t ena t decay
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 70 rev. pra figure 36 equivalent device loading for ac measurements (includes all fixtures) figure 37 voltage reference levels for ac measurements (except output enable/disable) capacitive loading output delays and holds are based on standard capacitive loads: 50 pf on all pins (see figure 36 on page 70 ). the delay and hold specifications given should be derated by a factor of 1.5 ns/50 pf for loads other than the nominal value of 50 pf. figures 31-32, 34-35 show how output rise time varies with capacitance. figures 33, 37 show graphically how output delays and holds vary with load capacitance (note that this graph or derating does not apply to output disable delays; see ? output disable time ? on page 69 .). the graphs of figures 31, 32 and 33 may not be linear outside the ranges shown. figure 38 adsp-21161n typical drive currents +1.5v 50pf to output pin i ol i oh input or output 1.5v 1.5v source (vddext) voltage - v 120 -20 -80 0 3.5 0.5 1 1.5 2 2.5 3 100 0 -40 -60 60 20 80 40 -100 -120 source (vddext) current - ma 3.47v, 0c 3.3v, +25c 3.13v, +85c v oh 3.13v, +85c 3.3v, +25c 3.47v, 0c v ol
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 71 rev. pra figure 39 typical output rise time (10%-90%, v ddext =max) vs. load capacitance figure 40 typical output rise time (10%-90%, v ddext =min) vs. load capacitance figure 41 typical output delay or hold vs. load capacitance (at max case temperature) load capacitance - pf 16.0 8.0 0 0 200 20 40 60 80 100 120 140 160 180 14.0 12.0 4.0 2.0 10.0 6.0 fall time rise time y = tbd y = tbd rise and fall tim es - ns (0.35v - 3.12v, 10% - 90 %) 3.5 0 3.0 2.5 2.0 1.5 1.0 0.5 load capacitance - pf 0 200 20 40 60 80 100 120 140 160 180 fall time rise time y = tbd y =tbd rise and fall times - ns (0.31 - 2.82, 10% - 90%) load capacitance - pf 5 - 25 200 50 75 100 125 150 175 4 3 2 1 nominal y = tbd output delay or ho ld - ns
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 72 rev. pra environmental conditions thermal characteristics the adsp-21161n is packaged in a 225-lead plastic ball grid array (pbga). the adsp-21161n is specified for a case temperature (t case ). to ensure that the t case data sheet specification is not exceeded, a heatsink and/or an air flow source may be used. use the center block of ground pins (pbga balls: f6-10, g6-10, h6-10, j6-10, k6-10) to provide thermal pathways to your printed circuit board ? s ground plane. a heatsink should be attached to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive. t case = t amb + (pd ca ) t case = case temperature (measured on top surface of package) pd = power dissipation in w (this value depends upon the specific application; a method for calculating pd is shown under power dissipation). ca = value from table below. jb = tbd c/w notes this represents thermal resistance at total power of tbd w. with air flow, no variance is seen in ca with power. ca at 0 lfm varies with power: at [data not available- tbd.] . jc = tbd c/w airflow (linear ft./min.) tbd tbd tbd tbd tbd airflow (meters/second) tbd tbd tbd tbd tbd ca ( c/w) 1 1. these are preliminary estimates. tbd tbd tbd tbd tbd
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 73 rev. pra 225-ball metric pbga pin configurations table 37 225-lead metric pbga pin assignments pin name pbga pin# pin name pbga pin# pin name pbga pin# pin name pbga pin# nc a01 trst_b b01 tms c01 tdo d01 bmstr a02 tdi b02 emu_b c02 tck d02 bms_b a03 rpba b03 gnd c03 flag11 d03 spids a04 mosi b04 spiclk c04 miso d04 eboot a05 sfs0 b05 sd0b c05 sclk0 d05 lboot a06 sclk1 b06 sd1a c06 sd1b d06 sclk2 a07 sd2b b07 sd2a c07 sfs1 d07 sd3b a08 sd3a b08 sfs2 c08 vddint d08 l0dat[4] a09 l0dat[7] b09 sfs3 c09 sclk3 d09 l0ack a10 l0clk b10 l0dat[6] c10 l0dat[5] d10 l0dat[2] a11 l0dat[1] b11 l1dat[7] c11 l0dat[3] d11 l1dat[6] a12 l1dat[4] b12 l1dat[3] c12 l1dat[5] d12 l1clk a13 l1ack b13 l1dat[1] c13 data[42] d13 l1dat[2] a14 l1dat[0] b14 data[45] c14 data[46] d14 nc a15 nc b15 data[47] c15 data[44] d15 flag10 e01 flag5 f01 flag1 g01 flag0 h01 reset_b e02 flag7 f02 flag2 g02 irq0_b h02 flag8 e03 flag9 f03 flag4 g03 vddint h03 sd0a e04 flag6 f04 flag3 g04 irq1_b h04 vddext e05 vddint f05 vddext g05 vddint h05 vddint e06 gnd f06 gnd g06 gnd h06 vddext e07 gnd f07 gnd g07 gnd h07 vddint e08 gnd f08 gnd g08 gnd h08 vddext e09 gnd f09 gnd g09 gnd h09 vddint e10 gnd f10 gnd g10 gnd h10 vddext e11 vddint f11 vddext g11 vddint h11 l0dat[0] e12 data[37] f12 data[34] g12 data[29] h12 data[39] e13 data[40] f13 data[35] g13 data[28] h13 data[43] e14 data[38] f14 data[33] g14 data[30] h14
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 74 rev. pra data[41] e15 data[36] f15 data[32] g15 data[31] h15 irq2_b j01 timexp k01 addr[19] l01 addr[16] m01 id1 j02 addr[22] k02 addr[17] l02 addr[12] m02 id2 j03 addr[20] k03 addr[21] l03 addr[18] m03 id0 j04 addr[23] k04 addr[2] l04 addr[6] m04 vddext j05 vddint k05 vddext l05 addr[0] m05 gnd j06 gnd k06 vddint l06 ms1_b m06 gnd j07 gnd k07 vddext l07 br6_b m07 gnd j08 gnd k08 vddint l08 vddext m08 gnd j09 gnd k09 vddext l09 wrl_b m09 gnd j10 gnd k10 vddint l10 sda10 m10 vddext j11 vddint k11 vddext l11 ras_b m11 data[26] j12 data[22] k12 cas_b l12 ack m12 data[24] j13 data[19] k13 data[20] l13 data[17] m13 data[25] j14 data[21] k14 data[16] l14 dmag2_b m14 data[27] j15 data[23] k15 data[18] l15 dmag1_b m15 addr[14] n01 addr[13] p01 nc r01 addr[15] n02 addr[9] p02 addr[11] r02 addr[10] n03 addr[8] p03 addr[7] r03 addr[5] n04 addr[4] p04 addr[3] r04 addr[1] n05 ms2_b p05 ms3_b r05 ms0_b n06 sbts_b p06 pa_b r06 br5_b n07 br4_b p07 br3_b r07 br2_b n08 br1_b p08 rdl_b r08 brst n09 sdclk1 p09 clkout r09 sdcke n10 sdclk0 p10 hbr_b r10 cs_b n11 redy p11 hbg_b r11 clk_cfg1 n12 clkin p12 clkdbl r12 clk_cfg0 n13 dqm p13 xtal r13 avdd n14 avss p14 sdwe_b r14 dmar1_b n15 dmar2_b p15 nc r15 table 37 225-lead metric pbga pin assignments (continued) pin name pbga pin# pin name pbga pin# pin name pbga pin# pin name pbga pin#
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 75 rev. pra figure 42 225-lead metric pbga pin assignments (bottom view, summary) vddint vddext gnd* avss avdd signal key: * use the center block of ground pins to p rovide therm a l pathways to your printed circuit board?s ground plane. 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 r p n m l k j h g f e d c b a
this information applies to a product under development. its characteristics and specifications are subject to change with- out notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. adsp-21161n preliminary data sheet july 2000 for current information contact analog devices at (781) 461-3881 76 rev. pra package dimensions the adsp-21161n comes in a 17mm 17mm, 225 ball pbga package with 15 rows of balls. all dimensions in figure 43 are in millimeters (mm). figure 43 package dimensions metric 17mm 17mm, 225 ball pbga ordering guide part number 1 1. these parts are packaged in a 225-lead plastic ball grid array (pbga). case temperature range 2 2. parts for the industrial temperature ranges will be available in 2000. instruction rate on-chip sram operating voltage ADSP-21161N-KB-100X 0 c to +85 c 100 mhz 1 mbit 1.8 int/3.3 ext v 1.00 bsc 14.00 bsc 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 r p n m l k j h g f e d c b a 1.00 bsc 14.00 bsc 17.20 17.00 16.80 17.20 17.00 16.80 14.80 15.00 15.20 14.80 15.00 15.20 top view 1.90 1.60 1.30 detail a note the actual position of the ball grid is within 0.30mm of its ideal position relative to the package edges. the actual position of each ball is within 0.10mm of its ideal position relative to the ball grid. seating plane .65 (min) .75 (typical) .85 (max) 0.20 max detail a 0.70 0.60 0.50 ball diameter 0.45 0.35 0.25 0.40 (min) 0.50 (typical) 0.60 (max) (bottom view) a1 ball pad corner

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